c6c973dbfa
The minimum supported GCC version is 8.1, which supports flag output operands and always defines __GCC_ASM_FLAG_OUTPUTS__ macro. Remove code depending on __GCC_ASM_FLAG_OUTPUTS__ and use the "=@ccCOND" flag output operand directly. Use the equivalent "=@ccz" instead of "=@cce" flag output operand for CMPXCHG8B and CMPXCHG16B instructions. These instructions set a single flag bit - the Zero flag - and "=@ccz" is used to distinguish the CC user from comparison instructions, where set ZERO flag indeed means that the values are equal. Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20250905121723.GCaLrU04lP2A50PT-B@fat_crate.local
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright 2007 rPath, Inc. - All Rights Reserved
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*
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* ----------------------------------------------------------------------- */
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/*
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* Very simple bitops for the boot code.
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*/
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#ifndef BOOT_BITOPS_H
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#define BOOT_BITOPS_H
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#define _LINUX_BITOPS_H /* Inhibit inclusion of <linux/bitops.h> */
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#include <linux/types.h>
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#include <asm/asm.h>
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static inline bool constant_test_bit(int nr, const void *addr)
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{
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const u32 *p = addr;
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return ((1UL << (nr & 31)) & (p[nr >> 5])) != 0;
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}
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static inline bool variable_test_bit(int nr, const void *addr)
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{
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bool v;
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const u32 *p = addr;
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asm("btl %2,%1" : "=@ccc" (v) : "m" (*p), "Ir" (nr));
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return v;
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}
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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constant_test_bit((nr),(addr)) : \
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variable_test_bit((nr),(addr)))
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static inline void set_bit(int nr, void *addr)
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{
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asm("btsl %1,%0" : "+m" (*(u32 *)addr) : "Ir" (nr));
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}
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#endif /* BOOT_BITOPS_H */
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