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Merge patch series "configs: phycore_am6xx_a53_defconfig: Enable CMD_DDR4"

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This series from Wadim Egorov <w.egorov@phytec.de> performs some
improvements to some of the phycore am6xx series devices.

Link: https://lore.kernel.org/r/20260113053531.1204984-1-w.egorov@phytec.de
This commit is contained in:
Tom Rini
2026-01-21 09:17:22 -06:00
parent 084faca1d7 c620865280
commit 019908a506
5 changed files with 3 additions and 2 deletions
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1
configs/phycore_am62ax_a53_defconfig
View File

@@ -78,6 +78,7 @@ CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_DDR4=y
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y

1
configs/phycore_am62ax_r5_ethboot_defconfig
View File

@@ -21,7 +21,6 @@ CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_PHY_TI_DP83867=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_SPL_MMC=n
CONFIG_SPL_DM_SPI=n

1
configs/phycore_am62x_a53_defconfig
View File

@@ -80,6 +80,7 @@ CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_DDR4=y
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y

1
configs/phycore_am62x_r5_ethboot_defconfig
View File

@@ -20,7 +20,6 @@ CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_PHY_TI_DP83867=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_SPL_MMC=n
CONFIG_SPL_DM_SPI=n

1
configs/phycore_am64x_a53_defconfig
View File

@@ -80,6 +80,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_DDR4=y
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y