From eb314cb566abe0c6eb675c9c857a0cd1bb8c5cf9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:25 +0200 Subject: [PATCH 01/17] imx: kontron-sl-mx6ul: Fix include statements for local header The header from the local directory should use double quotes instead of brackets. Otherwise the compiler might not search the local directory. Fixes: 93935acc6f1d ("imx: imx6ul: kontron-sl-mx6ul: Select correct boot and env device") Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul-common.c | 2 +- board/kontron/sl-mx6ul/sl-mx6ul.c | 3 ++- board/kontron/sl-mx6ul/spl.c | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/board/kontron/sl-mx6ul/sl-mx6ul-common.c b/board/kontron/sl-mx6ul/sl-mx6ul-common.c index 1f24acdfa3d..bda71a330ca 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul-common.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul-common.c @@ -6,7 +6,7 @@ #include #include -#include +#include "sl-mx6ul-common.h" bool sl_mx6ul_is_spi_nor_boot(void) { diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index 0f45ea84fc7..16d89c64d61 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -9,7 +9,8 @@ #include #include #include -#include + +#include "sl-mx6ul-common.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index 33e5337bcbc..8d55273dd9c 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -18,7 +18,8 @@ #include #include #include -#include + +#include "sl-mx6ul-common.h" DECLARE_GLOBAL_DATA_PTR; From 7118d961cccdb3cf86f3e2eebf19c476bba5aca9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:26 +0200 Subject: [PATCH 02/17] imx: kontron-sl-mx6ul: Enable standard boot and disable legacy distro boot Disable the legacy distro boot and use bootstd instead. Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 3 ++- include/configs/kontron-sl-mx6ul.h | 12 ------------ 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 9ee02259948..b04cd75a7d4 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -25,7 +25,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_FIXUP_PARTITIONS=y CONFIG_SYS_PBSIZE=532 @@ -50,6 +50,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y +CONFIG_CMD_SYSBOOT=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FS_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 015df01db4e..e2152eb05ed 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -24,22 +24,10 @@ /* Board and environment settings */ #define CFG_MXC_UART_BASE UART4_BASE -/* Boot order for distro boot */ -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0, UBI, boot) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#include - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CFG_EXTRA_ENV_SETTINGS BOOTENV - #endif /* __KONTRON_MX6UL_CONFIG_H */ From 8addeb94c72bfac9561a1bae3844a94c05cefb47 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:27 +0200 Subject: [PATCH 03/17] imx: kontron-sl-mx6ul: Set CONFIG_SDP_LOADADDR to fix SDP boot We need to set CONFIG_SDP_LOADADDR to a valid RAM address to make SDP boot work. Use the end of the DDR (256 MiB minimum) as other boards do. Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index b04cd75a7d4..7ecf2bbaa9f 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -107,5 +107,6 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x8f7fffc0 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y From 048fdda977abe8ebb51dfab7450f7a5b80465059 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:28 +0200 Subject: [PATCH 04/17] imx: kontron-sl-mx6ul: Enable second ethernet interface This ensures both interfaces can be used in U-Boot and both MAC addresses are exported to the Linux kernel devicetree. Signed-off-by: Frieder Schrempf --- arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi index 39cc6d05d3f..042bda7462a 100644 --- a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi @@ -30,9 +30,6 @@ * in Linux we can't assign the shared reset GPIO to the PHYs, as this * would cause Linux to reset both PHYs every time one of them gets * reinitialized. - * - * Also we disable the second ethernet as it currently doesn't work with - * the devicetree setup in U-Boot. */ &fec1 { @@ -53,11 +50,16 @@ clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; }; }; &fec2 { - status = "disabled"; - /delete-property/ phy-handle; /delete-node/ mdio; }; From f3406a2364eaac81735594d5cb6c10d38bd25c8f Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 25 Aug 2025 15:54:29 +0200 Subject: [PATCH 05/17] imx: kontron-sl-mx6ul: Enable fastboot support Enable support for fastboot commands via USB. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 7ecf2bbaa9f..1831f99db46 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTD_FULL=y @@ -69,6 +70,13 @@ CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="kontron-mx6ul" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_DM_I2C=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -108,5 +116,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x8f7fffc0 -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y From 6bd59313e0c9550e49d1973d664f896dab08c8f9 Mon Sep 17 00:00:00 2001 From: Oualid Derouiche Date: Mon, 25 Aug 2025 15:54:30 +0200 Subject: [PATCH 06/17] imx: kontron-sl-mx6ul: Enable redundant environment This aligns the MTD partitions on the SPI NOR with the kernel devicetree and enables the redundant environment. Signed-off-by: Oualid Derouiche Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 1831f99db46..a5ee4d67c00 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -7,9 +7,9 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF0000 -CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x4000 CONFIG_MX6UL=y CONFIG_TARGET_KONTRON_MX6UL=y CONFIG_DM_GPIO=y @@ -19,6 +19,7 @@ CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0xF8000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MEMTEST_START=0x80000000 @@ -56,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FS_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:960k(u-boot),32k(env),32k(env_redundant);spi4.0:-(UBI)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -64,6 +65,7 @@ CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" CONFIG_USE_HOSTNAME=y From 410d9ccc0388b77b1e21ba218b2e21138930c90f Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 25 Aug 2025 15:54:31 +0200 Subject: [PATCH 07/17] imx: kontron-sl-mx6ul: Autostart fastboot if booted from USB For booting via USB we want to automatically start the fastboot command in order to access the board via uuu or other tools. This allows for easier bringup of new boards during development and manufacturing. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index 16d89c64d61..e33907ee124 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -5,7 +5,9 @@ #include #include +#include #include +#include #include #include #include @@ -87,6 +89,16 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + if (is_boot_from_usb()) { + env_set("bootdelay", "0"); + env_set("bootcmd", "fastboot 0"); + } + + return 0; +} + enum env_location env_get_location(enum env_operation op, int prio) { if (prio) From 9e26426ceb0aacc52b3cf693fdeac3b13cb8e6f9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:32 +0200 Subject: [PATCH 08/17] imx: kontron-sl-mx6ul: Enable watchdog and sysreset Enable the watchdog and sysreset drivers and the wdt command. This also fixes the non-working 'reset' command. Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index a5ee4d67c00..fed29e77936 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -51,6 +51,7 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_SYSBOOT=y CONFIG_CMD_EXT4_WRITE=y @@ -107,6 +108,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y # CONFIG_FSL_QSPI_AHB_FULL_MAP is not set CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_SYSRESET_WATCHDOG_AUTO=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -119,3 +123,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x8f7fffc0 CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_IMX_WATCHDOG=y From 827e45f28ffb60eae4ce839d22121eda4c34a458 Mon Sep 17 00:00:00 2001 From: Eberhard Stoll Date: Mon, 25 Aug 2025 15:54:33 +0200 Subject: [PATCH 09/17] imx: kontron-sl-mx6ul: Enable CONFIG_ENV_IS_NOWHERE For some cases it is beneficial to not store the environment in persistent memory, but instead use the default environment and keep it in volatile RAM only. Allow this by enabling CONFIG_ENV_IS_NOWHERE. Signed-off-by: Eberhard Stoll Signed-off-by: Frieder Schrempf --- configs/kontron-sl-mx6ul_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index fed29e77936..052d7a76610 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -64,6 +64,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl" CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y From 6bfd81c3394cfa02d9e5d45e8ad4ca8634b177fe Mon Sep 17 00:00:00 2001 From: Eberhard Stoll Date: Mon, 25 Aug 2025 15:54:34 +0200 Subject: [PATCH 10/17] imx: kontron-sl-mx6ul: Force default environment for serial loader boot In case of booting from serial loader (USB) we want to always use the default environment in order to get a defined state that is independent of any environment stored in persistent memory. This way we can avoid corruption of the boot process during development and manufacturing by existing environment settings in flash. Signed-off-by: Eberhard Stoll Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index e33907ee124..65f9b75c1a0 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -104,10 +104,16 @@ enum env_location env_get_location(enum env_operation op, int prio) if (prio) return ENVL_UNKNOWN; + if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE) && is_boot_from_usb()) + return ENVL_NOWHERE; + if (sl_mx6ul_is_spi_nor_boot() && CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) return ENVL_SPI_FLASH; else if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) return ENVL_MMC; - return ENVL_NOWHERE; + if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + + return ENVL_UNKNOWN; } From 1f87a8ac6b3d1823b908615ff210065683fda805 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:35 +0200 Subject: [PATCH 11/17] imx: kontron-sl-mx6ul: Switch to OF_UPSTREAM Use the upstream devicetrees instead of the local ones. Signed-off-by: Frieder Schrempf [fabio: Remove imx6ul-kontron-bl.dtb and imx6ull-kontron-bl.dtb from Makefile] --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6ul-kontron-bl-43.dts | 103 ------ arch/arm/dts/imx6ul-kontron-bl-common.dtsi | 406 --------------------- arch/arm/dts/imx6ul-kontron-bl.dts | 16 - arch/arm/dts/imx6ul-kontron-sl-common.dtsi | 137 ------- arch/arm/dts/imx6ul-kontron-sl.dtsi | 14 - arch/arm/dts/imx6ull-kontron-bl.dts | 15 - arch/arm/dts/imx6ull-kontron-sl.dtsi | 13 - configs/kontron-sl-mx6ul_defconfig | 5 +- 9 files changed, 4 insertions(+), 709 deletions(-) delete mode 100644 arch/arm/dts/imx6ul-kontron-bl-43.dts delete mode 100644 arch/arm/dts/imx6ul-kontron-bl-common.dtsi delete mode 100644 arch/arm/dts/imx6ul-kontron-bl.dts delete mode 100644 arch/arm/dts/imx6ul-kontron-sl-common.dtsi delete mode 100644 arch/arm/dts/imx6ul-kontron-sl.dtsi delete mode 100644 arch/arm/dts/imx6ull-kontron-bl.dts delete mode 100644 arch/arm/dts/imx6ull-kontron-sl.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ff8f1ed1ac0..7ada4131ab2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -833,9 +833,7 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb \ - imx6ul-kontron-bl.dtb \ - imx6ull-kontron-bl.dtb + imx6ul-pico-pi.dtb dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ diff --git a/arch/arm/dts/imx6ul-kontron-bl-43.dts b/arch/arm/dts/imx6ul-kontron-bl-43.dts deleted file mode 100644 index 0c643706a15..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl-43.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul-kontron-bl.dts" - -/ { - model = "Kontron BL i.MX6UL 43 (N631X S 43)"; - compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul", - "kontron,sl-imx6ul", "fsl,imx6ul"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm7 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; -}; - -&i2c4 { - touchscreen@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cap_touch>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - /* Leave status disabled because of missing display panel node */ -}; - -&pwm7 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&iomuxc { - pinctrl_cap_touch: captouchgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */ - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common.dtsi deleted file mode 100644 index a6cf0f21c66..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "debug-led1"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "debug-led2"; - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "debug-led3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm8 0 5000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_adc: regulator-vref-adc { - compatible = "regulator-fixed"; - regulator-name = "vref-adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - num-channels = <3>; - vref-supply = <®_vref_adc>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - eeprom@0 { - compatible = "anvo,anv32e61w", "atmel,at25"; - reg = <0>; - spi-max-frequency = <20000000>; - spi-cpha; - spi-cpol; - pagesize = <1>; - size = <8192>; - address-width = <16>; - }; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&pwm8 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - rs485-rts-active-low; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 - >; - }; - - pinctrl_enet2_mdio: enet2mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 - /* - * mux unused RTS to make sure it doesn't cause - * any interrupts when it is undefined - */ - MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1 { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-bl.dts b/arch/arm/dts/imx6ul-kontron-bl.dts deleted file mode 100644 index dadf6d3d5f5..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -/dts-v1/; - -#include "imx6ul-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6UL (N631X S)"; - compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi b/arch/arm/dts/imx6ul-kontron-sl-common.dtsi deleted file mode 100644 index dcf88f61034..00000000000 --- a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - memory@80000000 { - reg = <0x80000000 0x10000000>; - device_type = "memory"; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec2 { - phy-mode = "rmii"; - status = "disabled"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - }; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_out>; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 - MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 - >; - }; - - pinctrl_enet1_mdio: enet1mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_reset_out: rstoutgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-sl.dtsi b/arch/arm/dts/imx6ul-kontron-sl.dtsi deleted file mode 100644 index 0580d043e5a..00000000000 --- a/arch/arm/dts/imx6ul-kontron-sl.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6UL (N631X SOM)"; - compatible = "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/dts/imx6ull-kontron-bl.dts b/arch/arm/dts/imx6ull-kontron-bl.dts deleted file mode 100644 index fa016465cdb..00000000000 --- a/arch/arm/dts/imx6ull-kontron-bl.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ull-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6ULL (N641X S)"; - compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/arch/arm/dts/imx6ull-kontron-sl.dtsi b/arch/arm/dts/imx6ull-kontron-sl.dtsi deleted file mode 100644 index 93f10eb3494..00000000000 --- a/arch/arm/dts/imx6ull-kontron-sl.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ull.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6ULL (N641X SOM)"; - compatible = "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 052d7a76610..8e35d894dae 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -13,7 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x4000 CONFIG_MX6UL=y CONFIG_TARGET_KONTRON_MX6UL=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-bl" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ul-kontron-bl" CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 @@ -62,7 +62,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:960k(u-boot),32k(env),32k(env_redundant CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl" +CONFIG_OF_UPSTREAM=y +CONFIG_OF_LIST="nxp/imx/imx6ul-kontron-bl nxp/imx/imx6ull-kontron-bl" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y From d95c4bebf40cddff5b284abfb591eb47f84ebb12 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 12 Aug 2025 09:08:06 +0300 Subject: [PATCH 12/17] tools: imx8image: Make imx8image_check_params() static We are trying to enable -Wmissing-prototypes and this functiion is only used locally. Mark it as static. Signed-off-by: Ilias Apalodimas Acked-by: Peng Fan --- tools/imx8image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imx8image.c b/tools/imx8image.c index 5a76643c06e..3cea536b8e8 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -23,7 +23,7 @@ static uint8_t cntr_version; static uint32_t custom_partition; static uint32_t scfw_flags; -int imx8image_check_params(struct image_tool_params *params) +static int imx8image_check_params(struct image_tool_params *params) { return 0; } From 8c690095b84741717598d6bbc39116c8028adbd9 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 21 Aug 2025 08:46:14 +0200 Subject: [PATCH 13/17] arm: dts: imx93-phyboard-segin-u-boot: Clean-up already upstream nodes Clean-up "imx93-phyboard-segin-u-boot.dtsi" internal device-tree from nodes already part of the upstream device-tree since commit 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream"). No functional change is made with this commit. Signed-off-by: Primoz Fiser --- arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 219 +++--------------- 1 file changed, 35 insertions(+), 184 deletions(-) diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 0c3ca2961c9..0c8d0ba9693 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -69,6 +69,16 @@ bootph-some-ram; }; +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; + bootph-some-ram; +}; + &pinctrl_reg_usdhc2_vmmc { bootph-pre-ram; }; @@ -83,6 +93,16 @@ bootph-some-ram; }; +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + &pinctrl_usdhc2_cd { bootph-pre-ram; bootph-some-ram; @@ -128,31 +148,9 @@ bootph-some-ram; }; -/* - * Remove once USB support is added to imx93-phyboard-segin.dts upstream. - */ -&usbotg1 { - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - &usdhc1 { bootph-pre-ram; bootph-some-ram; - /* - * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi - */ - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; }; &usdhc2 { @@ -174,6 +172,21 @@ &lpi2c3 { bootph-pre-ram; bootph-some-ram; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + }; + }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + }; }; &s4muap { @@ -209,165 +222,3 @@ bootph-all; bootph-pre-ram; }; - -/* - * The two nodes below won't be needed once nxp,pca9451a - * support is added to the Linux kernel. - */ -&iomuxc { - pinctrl_lpi2c3: lpi2c3grp { - bootph-pre-ram; - fsl,pins = < - MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - }; - - pinctrl_pmic: pmicgrp { - bootph-pre-ram; - fsl,pins = < - MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e - >; - }; - - /* - * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they - * are added to imx93-phycore-som.dtsi - */ - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - bootph-pre-ram; - bootph-some-ram; - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - bootph-pre-ram; - bootph-some-ram; - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; -}; - -&lpi2c3 { - bootph-pre-ram; - bootph-some-ram; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-1 = <&pinctrl_lpi2c3>; - status = "okay"; - - pmic@25 { - bootph-pre-ram; - bootph-some-ram; - compatible = "nxp,pca9451a"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - regulators { - bootph-pre-ram; - bootph-some-ram; - buck1: BUCK1 { - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <610000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "VDDQ_0V6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4: BUCK4 { - regulator-name = "VDD_3V3_BUCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "VDD_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "PMIC_SNVS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "VDD_0V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - bootph-pre-ram; - bootph-some-ram; - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - vcc-supply = <&buck4>; - }; -}; From d271a01dbeba746bb35c4a068afc3ccfc5fc91d5 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 28 Aug 2025 10:20:07 +0200 Subject: [PATCH 14/17] configs: imx93-phycore_defconfig: Disable CONFIG_AHAB_BOOT By default, lets disable configuration option CONFIG_AHAB_BOOT=y on the phyCORE-i.MX93 based boards. This option is only used in the secureboot context which is not provided by default anyway. Lets remove it from the defconfig to not give false impressions it is supported out of the box for this board. On the other hand, in the context of PHYTEC secureboot, this option is selected by the distro which enables CONFIG_AHAB_BOOT among other secure boot related options and tweaks needed to properly support it. Signed-off-by: Primoz Fiser Reviewed-by: Martin Schwan --- configs/imx93-phycore_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index af149128ed4..53cd28dfcba 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -13,7 +13,6 @@ CONFIG_ENV_OFFSET=0x700000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-phyboard-segin" -CONFIG_AHAB_BOOT=y CONFIG_TARGET_PHYCORE_IMX93=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_MONITOR_LEN=524288 From b4ab315a0a5c32607d0d12734d0d3cb03d813e8b Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 28 Aug 2025 10:20:08 +0200 Subject: [PATCH 15/17] board: phytec: phycore-imx93: Use CONFIG_PHYTEC_EEPROM_BUS Switch to use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value of 2 for the EEPROM I2C bus for both SPL and U-Boot proper. Possible since commit 88a1816a9b4e ("board: phytec: common: Add PHYTEC_EEPROM_BUS to Kconfig"). Signed-off-by: Primoz Fiser Reviewed-by: Wadim Egorov --- board/phytec/phycore_imx93/phycore-imx93.c | 2 +- board/phytec/phycore_imx93/spl.c | 2 +- configs/imx93-phycore_defconfig | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index fab66caf2a1..c6a4e923b07 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); + int ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret) printf("%s: EEPROM data init failed\n", __func__); diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index beaa536c600..7feee4bcf6f 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -52,7 +52,7 @@ void spl_dram_init(void) int ret; enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; - ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) goto out; diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 53cd28dfcba..0acdfd2bf53 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_PHYTEC_EEPROM_BUS=2 CONFIG_ENV_SOURCE_FILE="phycore_imx93" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x700000 From 5d75b4f8767d4e27ea4074f2b06bec2d6f78bfb4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Aug 2025 16:28:15 -0300 Subject: [PATCH 16/17] imx8m[m,n,p]_evk: Add redundant environment support For reliable Over The Air update, it is recommended that redundant environment is used. Add redundant environment support for the i.MX8M EVK boards. While at it, increase the environment size and adjust the offset. Signed-off-by: Fabio Estevam --- configs/imx8mn_ddr4_evk_defconfig | 6 ++++-- configs/imx8mn_evk_defconfig | 6 ++++-- configs/imx8mp_evk_defconfig | 6 ++++-- configs/imx8mq_evk_defconfig | 6 ++++-- 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index a80ceab56f5..c0c22f99078 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-ddr4-evk" CONFIG_TARGET_IMX8MN_DDR4_EVK=y @@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -64,6 +65,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 47a30946818..0d6d31abba3 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-evk" CONFIG_TARGET_IMX8MN_EVK=y @@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_EFI_SET_TIME=y CONFIG_EFI_MM_COMM_TEE=y @@ -82,6 +83,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 0ad1acb94b6..5c3c8a2ca57 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-evk" CONFIG_TARGET_IMX8MP_EVK=y @@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x20400 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_VAR_BUF_SIZE=139264 @@ -77,6 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 21bb04d18a8..10de69689e9 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x600000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -25,6 +25,7 @@ CONFIG_SPL_BSS_START_ADDR=0x180000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_IMX_BOOTAUX=y CONFIG_REMAKE_ELF=y CONFIG_EFI_MM_COMM_TEE=y @@ -75,6 +76,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y From 28d6f787b0deb3f66118857297a855233eba18d1 Mon Sep 17 00:00:00 2001 From: Benjamin Hahn Date: Tue, 2 Sep 2025 08:07:32 +0200 Subject: [PATCH 17/17] Add imx8mp-libra-fpsc board Add new imx8mp-libra-fpsc board. Bootph tags as well as USB device tree nodes are in u-boot.dtsi for now and will be removed when upstreamed. The Libra i.MX 8M Plus FPSC is a single board computer. It uses an i.MX 8M Plus FPSC [1] System on Module which utilizes the FPSC standard [2]. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc Signed-off-by: Benjamin Hahn Reviewed-by: Teresa Remmet Tested-by: Teresa Remmet Signed-off-by: Yannic Moog --- .../arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi | 131 ++ arch/arm/mach-imx/imx8m/Kconfig | 10 + board/phytec/imx8mp-libra-fpsc/Kconfig | 16 + board/phytec/imx8mp-libra-fpsc/MAINTAINERS | 9 + board/phytec/imx8mp-libra-fpsc/Makefile | 10 + .../imx8mp-libra-fpsc/imx8mp-libra-fpsc.c | 89 + .../imx8mp-libra-fpsc/imx8mp-libra-fpsc.env | 19 + .../imx8mp-libra-fpsc/imximage-8mp-sd.cfg | 9 + .../phytec/imx8mp-libra-fpsc/lpddr4_timing.c | 1813 +++++++++++++++++ board/phytec/imx8mp-libra-fpsc/spl.c | 132 ++ configs/imx8mp-libra-fpsc_defconfig | 175 ++ doc/board/phytec/imx8mp-libra-fpsc.rst | 83 + doc/board/phytec/index.rst | 1 + include/configs/imx8mp-libra-fpsc.h | 27 + 14 files changed, 2524 insertions(+) create mode 100644 arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi create mode 100644 board/phytec/imx8mp-libra-fpsc/Kconfig create mode 100644 board/phytec/imx8mp-libra-fpsc/MAINTAINERS create mode 100644 board/phytec/imx8mp-libra-fpsc/Makefile create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env create mode 100644 board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg create mode 100644 board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c create mode 100644 board/phytec/imx8mp-libra-fpsc/spl.c create mode 100644 configs/imx8mp-libra-fpsc_defconfig create mode 100644 doc/board/phytec/imx8mp-libra-fpsc.rst create mode 100644 include/configs/imx8mp-libra-fpsc.h diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi new file mode 100644 index 00000000000..1320f1540ed --- /dev/null +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc2", "mmc1", "ethernet"; + + efi { + compatible = "u-boot,distro-efi"; + }; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart4 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&uart4 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; +}; + +/* USB1 Type-C */ +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + fsl,power-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + vbus-supply = <®_vdd_5v0>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&usdhc3 { + bootph-pre-ram; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 74416a78847..e7bc154b805 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -345,6 +345,15 @@ config TARGET_PHYCORE_IMX8MP select IMX8M_LPDDR4 imply OF_UPSTREAM +config TARGET_IMX8MP_LIBRA_FPSC + bool "PHYTEC Libra i.MX 8M Plus FPSC" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + imply OF_UPSTREAM + help + Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC. + config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" select IMX8MM @@ -409,6 +418,7 @@ source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/msc/sm2s_imx8mp/Kconfig" source "board/mntre/imx8mq_reform2/Kconfig" +source "board/phytec/imx8mp-libra-fpsc/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/polyhex/imx8mp_debix_model_a/Kconfig" diff --git a/board/phytec/imx8mp-libra-fpsc/Kconfig b/board/phytec/imx8mp-libra-fpsc/Kconfig new file mode 100644 index 00000000000..4961611f7b2 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Kconfig @@ -0,0 +1,16 @@ +if TARGET_IMX8MP_LIBRA_FPSC + +config SYS_BOARD + default "imx8mp-libra-fpsc" + +config SYS_VENDOR + default "phytec" + +config IMX_CONFIG + default "board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg" + +config SYS_CONFIG_NAME + default "imx8mp-libra-fpsc" + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/imx8mp-libra-fpsc/MAINTAINERS b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS new file mode 100644 index 00000000000..1fd99888a2e --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS @@ -0,0 +1,9 @@ +Libra-i.MX 8M Plus +M: Teresa Remmet +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ +S: Maintained +F: arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi +F: board/phytec/imx8mp-libra-fpsc/ +F: configs/imx8mp-libra-fpsc_defconfig +F: include/configs/imx8mp-libra-fpsc.h +F: doc/board/phytec/imx8mp-libra-fpsc.rst diff --git a/board/phytec/imx8mp-libra-fpsc/Makefile b/board/phytec/imx8mp-libra-fpsc/Makefile new file mode 100644 index 00000000000..21b35d9142f --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2025 PHYTEC Messtechnik GmbH + +obj-y += imx8mp-libra-fpsc.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c new file mode 100644 index 00000000000..ffa21da1b34 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EEPROM_ADDR 0x51 + +#define TUSB_PORT_POL_CRTL_REG 0xB +#define TUSB_CUSTOM_POL BIT(7) +#define TUSB_P0_POL BIT(0) + +/* + * WORKAROUND for PCM-937-L 1618.0, 1618.1. + * USB HUB TUSB8042A has swapped upstream pin polarity. + * Set i2c registers to inform the hub that the lines + * are swapped. + */ +void tusb8042a_swap_lines(void) +{ + const u8 pol_swap_val = (TUSB_CUSTOM_POL | TUSB_P0_POL); + const int addr = 0x44; + struct udevice *dev = 0; + int ret = i2c_get_chip_for_busnum(2, addr, 1, &dev); + + if (!ret) + dm_i2c_write(dev, TUSB_PORT_POL_CRTL_REG, &pol_swap_val, 1); + else + printf("TUSB8042A: Failed to fixup USB HUB.\n"); +} + +int board_init(void) +{ + tusb8042a_swap_lines(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + switch (get_boot_device()) { + case SD2_BOOT: + env_set_ulong("mmcdev", 1); + if (!strcmp(env_get("boot_targets"), env_get_default("boot_targets"))) + env_set("boot_targets", "mmc1 mmc2 ethernet"); + break; + case MMC3_BOOT: + env_set_ulong("mmcdev", 2); + break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) + env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); + break; + default: + break; + } + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env new file mode 100644 index 00000000000..c744248ab7a --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env @@ -0,0 +1,19 @@ +boot_script_dhcp=boot.scr.uimg +console=ttymxc3,CONFIG_BAUDRATE +emmc_dev=2 /* This is needed by built-in uuu flash scripts */ +fdtfile=CONFIG_DEFAULT_FDT_FILE +fdt_addr_r=0x40480000 +fdt_overlay_addr_r=0x404a0000 +fit_fdtconf=conf-imx8mp-libra-rdk-fpsc.dtb +kernel_addr_r=0x40a00000 +kernel_comp_addr_r=0x43a00000 +kernel_comp_size=0x1e00000 +mmcroot=2 +pxefile_addr_r=0x45800000 +ramdisk_addr_r=0x45802000 +scriptaddr=0x47600000 +script_offset_f=0x0 +script_size_f=0x2000 +sd_dev=1 /* This is needed by built-in uuu flash scripts */ +ip_dyn=yes +nfsroot=/srv/nfs diff --git a/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg new file mode 100644 index 00000000000..6dedf1724ab --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c new file mode 100644 index 00000000000..1b501828726 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c @@ -0,0 +1,1813 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.5.0_9-1ddf053d. + * DDR PHY FW2020.06 + */ + +#include +#include + +/* Initialize DDRC registers */ +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa1080020}, + {0x3d400020, 0x1323}, + {0x3d400024, 0x1e84800}, + {0x3d400064, 0x7a0118}, + {0x3d400070, 0x7027f90}, + {0x3d400074, 0x790}, + {0x3d4000d0, 0xc00307a3}, + {0x3d4000d4, 0xc50000}, + {0x3d4000dc, 0xf4003f}, + {0x3d4000e0, 0xe30000}, + {0x3d4000e8, 0x440048}, + {0x3d4000ec, 0x140048}, + {0x3d400100, 0x2028222a}, + {0x3d400104, 0x8083f}, + {0x3d40010c, 0xe0e000}, + {0x3d400110, 0x12040a12}, + {0x3d400114, 0x2050f0f}, + {0x3d400118, 0x1010009}, + {0x3d40011c, 0x502}, + {0x3d400130, 0x20800}, + {0x3d400134, 0xe100002}, + {0x3d400138, 0x120}, + {0x3d400144, 0xc80064}, + {0x3d400180, 0x3e8001e}, + {0x3d400184, 0x3207a12}, + {0x3d400188, 0x0}, + {0x3d400190, 0x4a3820e}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x230e}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x7}, + {0x3d4001c4, 0x1}, + {0x3d4000f4, 0x799}, + {0x3d400108, 0x9141d1c}, + {0x3d400200, 0x1f}, + {0x3d400208, 0x0}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, + {0x3d400250, 0x1705}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400404, 0x72ff}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x18}, + {0x2002e, 0x2}, + {0x90204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x20056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x1204d, 0x600}, + {0x1214d, 0x600}, + {0x1304d, 0x600}, + {0x1314d, 0x600}, + {0x10049, 0x618}, + {0x10149, 0x618}, + {0x11049, 0x618}, + {0x11149, 0x618}, + {0x12049, 0x618}, + {0x12149, 0x618}, + {0x13049, 0x618}, + {0x13149, 0x618}, + {0x43, 0x21}, + {0x1043, 0x21}, + {0x2043, 0x21}, + {0x3043, 0x21}, + {0x4043, 0x21}, + {0x5043, 0x21}, + {0x6043, 0x21}, + {0x7043, 0x21}, + {0x8043, 0x21}, + {0x9043, 0x21}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x3e8}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x200fa, 0x1}, + {0x20019, 0x1}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5555}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x1}, + {0x2002c, 0x0}, +}; + +/* PHY trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x1205f, 0x0}, + {0x1215f, 0x0}, + {0x1305f, 0x0}, + {0x1315f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x3055, 0x0}, + {0x4055, 0x0}, + {0x5055, 0x0}, + {0x6055, 0x0}, + {0x7055, 0x0}, + {0x8055, 0x0}, + {0x9055, 0x0}, + {0x200c5, 0x0}, + {0x2002e, 0x0}, + {0x90204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x20056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x1204d, 0x0}, + {0x1214d, 0x0}, + {0x1304d, 0x0}, + {0x1314d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x12049, 0x0}, + {0x12149, 0x0}, + {0x13049, 0x0}, + {0x13149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x3043, 0x0}, + {0x4043, 0x0}, + {0x5043, 0x0}, + {0x6043, 0x0}, + {0x7043, 0x0}, + {0x8043, 0x0}, + {0x9043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x20008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x12043, 0x0}, + {0x12143, 0x0}, + {0x13043, 0x0}, + {0x13143, 0x0}, + {0x200fa, 0x0}, + {0x20019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x400fd, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x12011, 0x0}, + {0x12012, 0x0}, + {0x12013, 0x0}, + {0x12018, 0x0}, + {0x12002, 0x0}, + {0x120b2, 0x0}, + {0x121b4, 0x0}, + {0x122b4, 0x0}, + {0x123b4, 0x0}, + {0x124b4, 0x0}, + {0x125b4, 0x0}, + {0x126b4, 0x0}, + {0x127b4, 0x0}, + {0x128b4, 0x0}, + {0x13011, 0x0}, + {0x13012, 0x0}, + {0x13013, 0x0}, + {0x13018, 0x0}, + {0x13002, 0x0}, + {0x130b2, 0x0}, + {0x131b4, 0x0}, + {0x132b4, 0x0}, + {0x133b4, 0x0}, + {0x134b4, 0x0}, + {0x135b4, 0x0}, + {0x136b4, 0x0}, + {0x137b4, 0x0}, + {0x138b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x12068, 0x0}, + {0x12069, 0x0}, + {0x12168, 0x0}, + {0x12169, 0x0}, + {0x12268, 0x0}, + {0x12269, 0x0}, + {0x12368, 0x0}, + {0x12369, 0x0}, + {0x12468, 0x0}, + {0x12469, 0x0}, + {0x12568, 0x0}, + {0x12569, 0x0}, + {0x12668, 0x0}, + {0x12669, 0x0}, + {0x12768, 0x0}, + {0x12769, 0x0}, + {0x12868, 0x0}, + {0x12869, 0x0}, + {0x120aa, 0x0}, + {0x12062, 0x0}, + {0x12001, 0x0}, + {0x120a0, 0x0}, + {0x120a1, 0x0}, + {0x120a2, 0x0}, + {0x120a3, 0x0}, + {0x120a4, 0x0}, + {0x120a5, 0x0}, + {0x120a6, 0x0}, + {0x120a7, 0x0}, + {0x13068, 0x0}, + {0x13069, 0x0}, + {0x13168, 0x0}, + {0x13169, 0x0}, + {0x13268, 0x0}, + {0x13269, 0x0}, + {0x13368, 0x0}, + {0x13369, 0x0}, + {0x13468, 0x0}, + {0x13469, 0x0}, + {0x13568, 0x0}, + {0x13569, 0x0}, + {0x13668, 0x0}, + {0x13669, 0x0}, + {0x13768, 0x0}, + {0x13769, 0x0}, + {0x13868, 0x0}, + {0x13869, 0x0}, + {0x130aa, 0x0}, + {0x13062, 0x0}, + {0x13001, 0x0}, + {0x130a0, 0x0}, + {0x130a1, 0x0}, + {0x130a2, 0x0}, + {0x130a3, 0x0}, + {0x130a4, 0x0}, + {0x130a5, 0x0}, + {0x130a6, 0x0}, + {0x130a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x3080, 0x0}, + {0x4080, 0x0}, + {0x5080, 0x0}, + {0x6080, 0x0}, + {0x7080, 0x0}, + {0x8080, 0x0}, + {0x9080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x12020, 0x0}, + {0x12080, 0x0}, + {0x12081, 0x0}, + {0x120d0, 0x0}, + {0x120d1, 0x0}, + {0x1208c, 0x0}, + {0x1208d, 0x0}, + {0x12180, 0x0}, + {0x12181, 0x0}, + {0x121d0, 0x0}, + {0x121d1, 0x0}, + {0x1218c, 0x0}, + {0x1218d, 0x0}, + {0x120c0, 0x0}, + {0x120c1, 0x0}, + {0x121c0, 0x0}, + {0x121c1, 0x0}, + {0x122c0, 0x0}, + {0x122c1, 0x0}, + {0x123c0, 0x0}, + {0x123c1, 0x0}, + {0x124c0, 0x0}, + {0x124c1, 0x0}, + {0x125c0, 0x0}, + {0x125c1, 0x0}, + {0x126c0, 0x0}, + {0x126c1, 0x0}, + {0x127c0, 0x0}, + {0x127c1, 0x0}, + {0x128c0, 0x0}, + {0x128c1, 0x0}, + {0x120ae, 0x0}, + {0x120af, 0x0}, + {0x13020, 0x0}, + {0x13080, 0x0}, + {0x13081, 0x0}, + {0x130d0, 0x0}, + {0x130d1, 0x0}, + {0x1308c, 0x0}, + {0x1308d, 0x0}, + {0x13180, 0x0}, + {0x13181, 0x0}, + {0x131d0, 0x0}, + {0x131d1, 0x0}, + {0x1318c, 0x0}, + {0x1318d, 0x0}, + {0x130c0, 0x0}, + {0x130c1, 0x0}, + {0x131c0, 0x0}, + {0x131c1, 0x0}, + {0x132c0, 0x0}, + {0x132c1, 0x0}, + {0x133c0, 0x0}, + {0x133c1, 0x0}, + {0x134c0, 0x0}, + {0x134c1, 0x0}, + {0x135c0, 0x0}, + {0x135c1, 0x0}, + {0x136c0, 0x0}, + {0x136c1, 0x0}, + {0x137c0, 0x0}, + {0x137c1, 0x0}, + {0x138c0, 0x0}, + {0x138c1, 0x0}, + {0x130ae, 0x0}, + {0x130af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + {0x12040, 0x0}, + {0x12140, 0x0}, + {0x12240, 0x0}, + {0x12340, 0x0}, + {0x12440, 0x0}, + {0x12540, 0x0}, + {0x12640, 0x0}, + {0x12740, 0x0}, + {0x12840, 0x0}, + {0x13040, 0x0}, + {0x13140, 0x0}, + {0x13240, 0x0}, + {0x13340, 0x0}, + {0x13440, 0x0}, + {0x13540, 0x0}, + {0x13640, 0x0}, + {0x13740, 0x0}, + {0x13840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x8}, + {0x90159, 0xe8}, + {0x9015a, 0x109}, + {0x9015b, 0x0}, + {0x9015c, 0x8140}, + {0x9015d, 0x10c}, + {0x9015e, 0x10}, + {0x9015f, 0x8138}, + {0x90160, 0x104}, + {0x90161, 0x8}, + {0x90162, 0x448}, + {0x90163, 0x109}, + {0x90164, 0xf}, + {0x90165, 0x7c0}, + {0x90166, 0x109}, + {0x90167, 0x0}, + {0x90168, 0xe8}, + {0x90169, 0x109}, + {0x9016a, 0x47}, + {0x9016b, 0x630}, + {0x9016c, 0x109}, + {0x9016d, 0x8}, + {0x9016e, 0x618}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0xe0}, + {0x90172, 0x109}, + {0x90173, 0x0}, + {0x90174, 0x7c8}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x8140}, + {0x90178, 0x10c}, + {0x90179, 0x0}, + {0x9017a, 0x478}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x1}, + {0x9017e, 0x8}, + {0x9017f, 0x8}, + {0x90180, 0x4}, + {0x90181, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x68}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x7d}, + {0x2000c, 0xfa}, + {0x2000d, 0x9c4}, + {0x2000e, 0x2c}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, }, +}; diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c new file mode 100644 index 00000000000..d704d588579 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) +#include "../common/imx8m_som_detection.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define EEPROM_ADDR 0x51 + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + int ret; + + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR); + if (!ret) { + ret = phytec_imx8m_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + } +#endif + + ddr_init(&dram_timing); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_pca9450_init(0, 0x25); + if (ret) + printf("power init failed"); + p = pmic_get("PCA9450"); + pmic_probe(p); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + + /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set WDOG_B_CFG to cold reset */ + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +void spl_board_init(void) +{ + arch_misc_init(); + + /* Set GIC clock to 500Mhz for OD VDD_SOC. */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig new file mode 100644 index 00000000000..a23e604425d --- /dev/null +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x3C0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc" +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 +CONFIG_TARGET_IMX8MP_LIBRA_FPSC=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SYS_LOAD_ADDR=0x47602000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3e0000 +CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_FDT_FIXUP_PARTITIONS=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-libra-rdk-fpsc.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_REG=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x13000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_POWER_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_IMX_WATCHDOG=y diff --git a/doc/board/phytec/imx8mp-libra-fpsc.rst b/doc/board/phytec/imx8mp-libra-fpsc.rst new file mode 100644 index 00000000000..26752ac1882 --- /dev/null +++ b/doc/board/phytec/imx8mp-libra-fpsc.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Libra i.MX 8M Plus FPSC +======================= + +The Libra i.MX 8M Plus FPSC is a SBC based with the phyCORE-i.MX 8M Plus FPSC +SoM. +The phyCORE-i.MX 8M Plus FPSC with 2GB of main memory is supported. + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Build the OP-TEE binary +- Get ddr firmware +- Build U-Boot +- Boot + +Build the ARM Trusted firmware binary +------------------------------------- + +.. code-block:: bash + + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + PLAT=imx8mp \ + IMX_BOOT_UART_BASE=0x30a60000 \ + BL32_BASE=0x7e000000 \ + SPD=opteed \ + bl31 + +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + CFG_TEE_BENCHMARK=n \ + O=out/arm \ + PLATFORM=imx-mx8mp_libra_fpsc + +Get the ddr firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ chmod +x firmware-imx-8.28-994fa14.bin + $ ./firmware-imx-8.28-994fa14.bin + +Build U-Boot for SD card +------------------------ + +Copy binaries +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ cp /build/imx8mp/release/bl31.bin . + $ cp /out/arm/core/tee-raw.bin tee.bin + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + imx8mp-libra-fpsc_defconfig \ + flash.bin + +Flash SD card +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=fsync diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 1ae30c2dcd5..e24040a496e 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -6,6 +6,7 @@ PHYTEC .. toctree:: :maxdepth: 2 + imx8mp-libra-fpsc imx8mm-phygate-tauri-l imx93-phycore phycore-am62x diff --git a/include/configs/imx8mp-libra-fpsc.h b/include/configs/imx8mp-libra-fpsc.h new file mode 100644 index 00000000000..cde91dc3642 --- /dev/null +++ b/include/configs/imx8mp-libra-fpsc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#ifndef __IMX8MP_LIBRA_FPSC_H +#define __IMX8MP_LIBRA_FPSC_H + +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K + +#define CFG_SYS_SDRAM_BASE 0x40000000 + +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ + +#endif /* __IMX8MP_LIBRA_FPSC_H */