From c2ef9e1b0cb7e32a8046e4714a219fd21b9a0daf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 12 Nov 2025 14:00:02 -0600 Subject: [PATCH 1/7] video: mali_dp: Remove unused driver This driver is unused. Remove it. Signed-off-by: Tom Rini --- drivers/video/Kconfig | 8 - drivers/video/Makefile | 1 - drivers/video/mali_dp.c | 401 ---------------------------------------- 3 files changed, 410 deletions(-) delete mode 100644 drivers/video/mali_dp.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index b5777da5218..a12df55f84f 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -886,14 +886,6 @@ config VIDEO_IVYBRIDGE_IGD source "drivers/video/rockchip/Kconfig" -config VIDEO_ARM_MALIDP - bool "Enable Arm Mali Display Processor support" - depends on OF_CONTROL - select VEXPRESS_CLK - help - This enables support for Arm Ltd Mali Display Processors from - the DP500, DP550 and DP650 family. - config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" depends on SANDBOX_SDL diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 96c7ce7bb09..4189b81ba6b 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o -obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_BOCHS) += bochs.o obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c deleted file mode 100644 index c8921267462..00000000000 --- a/drivers/video/mali_dp.c +++ /dev/null @@ -1,401 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016-2018 ARM Ltd. - * Author: Liviu Dudau - * - */ -#define DEBUG -#include -#include -#include -#ifdef CONFIG_DISPLAY -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MALIDP_CORE_ID 0x0018 -#define MALIDP_REG_BG_COLOR 0x0044 -#define MALIDP_LAYER_LV1 0x0100 -#define MALIDP_DC_STATUS 0xc000 -#define MALIDP_DC_CONTROL 0xc010 -#define MALIDP_DC_CFG_VALID 0xc014 - -/* offsets inside the modesetting register block */ -#define MALIDP_H_INTERVALS 0x0000 -#define MALIDP_V_INTERVALS 0x0004 -#define MALIDP_SYNC_CONTROL 0x0008 -#define MALIDP_HV_ACTIVESIZE 0x000c -#define MALIDP_OUTPUT_DEPTH 0x001c - -/* offsets inside the layer register block */ -#define MALIDP_LAYER_FORMAT 0x0000 -#define MALIDP_LAYER_CONTROL 0x0004 -#define MALIDP_LAYER_IN_SIZE 0x000c -#define MALIDP_LAYER_CMP_SIZE 0x0010 -#define MALIDP_LAYER_STRIDE 0x0018 -#define MALIDP_LAYER_PTR_LOW 0x0024 -#define MALIDP_LAYER_PTR_HIGH 0x0028 - -/* offsets inside the IRQ control blocks */ -#define MALIDP_REG_MASKIRQ 0x0008 -#define MALIDP_REG_CLEARIRQ 0x000c - -#define M1BITS 0x0001 -#define M2BITS 0x0003 -#define M4BITS 0x000f -#define M8BITS 0x00ff -#define M10BITS 0x03ff -#define M12BITS 0x0fff -#define M13BITS 0x1fff -#define M16BITS 0xffff -#define M17BITS 0x1ffff - -#define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0) -#define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16) -#define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0) -#define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16) -#define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0) -#define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16) -#define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0) -#define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16) - -#define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16) -#define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0) - -#define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16) -#define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0) - -#define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16 -#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS) - -#define MALIDP_FORMAT_ARGB8888 0x08 -#define MALIDP_DEFAULT_BG_R 0x0 -#define MALIDP_DEFAULT_BG_G 0x0 -#define MALIDP_DEFAULT_BG_B 0x0 - -#define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16) - -#define MALIDP500 0x500 - -DECLARE_GLOBAL_DATA_PTR; - -struct malidp_priv { - phys_addr_t base_addr; - phys_addr_t dc_status_addr; - phys_addr_t dc_control_addr; - phys_addr_t cval_addr; - struct udevice *display; /* display device attached */ - struct clk aclk; - struct clk pxlclk; - u16 modeset_regs_offset; - u8 config_bit_shift; - u8 clear_irq; /* offset for IRQ clear register */ -}; - -static const struct video_ops malidp_ops = { -}; - -static int malidp_get_hwid(phys_addr_t base_addr) -{ - int hwid; - - /* - * reading from the old CORE_ID offset will always - * return 0x5000000 on DP500 - */ - hwid = readl(base_addr + MALIDP_CORE_ID); - if (MALIDP_PRODUCT_ID(hwid) == MALIDP500) - return hwid; - /* otherwise try the other gen CORE_ID offset */ - hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID); - - return hwid; -} - -/* - * wait for config mode bit setup to be acted upon by the hardware - */ -static int malidp_wait_configdone(struct malidp_priv *malidp) -{ - u32 status, tries = 300; - - while (tries--) { - status = readl(malidp->dc_status_addr); - if ((status >> malidp->config_bit_shift) & 1) - break; - udelay(500); - } - - if (!tries) - return -ETIMEDOUT; - - return 0; -} - -/* - * signal the hardware to enter configuration mode - */ -static int malidp_enter_config(struct malidp_priv *malidp) -{ - setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift); - return malidp_wait_configdone(malidp); -} - -/* - * signal the hardware to exit configuration mode - */ -static int malidp_leave_config(struct malidp_priv *malidp) -{ - clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift); - return malidp_wait_configdone(malidp); -} - -static void malidp_setup_timings(struct malidp_priv *malidp, - struct display_timing *timings) -{ - u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) | - MALIDP_V_SYNCWIDTH(timings->vsync_len.typ); - writel(val, malidp->base_addr + malidp->modeset_regs_offset + - MALIDP_SYNC_CONTROL); - val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) | - MALIDP_H_FRONTPORCH(timings->hfront_porch.typ); - writel(val, malidp->base_addr + malidp->modeset_regs_offset + - MALIDP_H_INTERVALS); - val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) | - MALIDP_V_FRONTPORCH(timings->vfront_porch.typ); - writel(val, malidp->base_addr + malidp->modeset_regs_offset + - MALIDP_V_INTERVALS); - val = MALIDP_H_ACTIVE(timings->hactive.typ) | - MALIDP_V_ACTIVE(timings->vactive.typ); - writel(val, malidp->base_addr + malidp->modeset_regs_offset + - MALIDP_HV_ACTIVESIZE); - /* default output bit-depth per colour is 8 bits */ - writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset + - MALIDP_OUTPUT_DEPTH); -} - -static int malidp_setup_mode(struct malidp_priv *malidp, - struct display_timing *timings) -{ - int err; - - if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0) - return -EIO; - - malidp_setup_timings(malidp, timings); - - err = display_enable(malidp->display, 8, timings); - if (err) - printf("display_enable failed with %d\n", err); - - return err; -} - -static void malidp_setup_layer(struct malidp_priv *malidp, - struct display_timing *timings, - u32 layer_offset, phys_addr_t fb_addr) -{ - u32 val; - - /* setup the base layer's pixel format to A8R8G8B8 */ - writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset + - MALIDP_LAYER_FORMAT); - /* setup layer composition size */ - val = MALIDP_CMP_V_SIZE(timings->vactive.typ) | - MALIDP_CMP_H_SIZE(timings->hactive.typ); - writel(val, malidp->base_addr + layer_offset + - MALIDP_LAYER_CMP_SIZE); - /* setup layer input size */ - val = MALIDP_IN_V_SIZE(timings->vactive.typ) | - MALIDP_IN_H_SIZE(timings->hactive.typ); - writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE); - /* setup layer stride in bytes */ - writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset + - MALIDP_LAYER_STRIDE); - /* set framebuffer address */ - writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset + - MALIDP_LAYER_PTR_LOW); - writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset + - MALIDP_LAYER_PTR_HIGH); - /* enable layer */ - setbits_le32(malidp->base_addr + layer_offset + - MALIDP_LAYER_CONTROL, 1); -} - -static void malidp_set_configvalid(struct malidp_priv *malidp) -{ - setbits_le32(malidp->cval_addr, 1); -} - -static int malidp_update_timings_from_edid(struct udevice *dev, - struct display_timing *timings) -{ -#ifdef CONFIG_DISPLAY - struct malidp_priv *priv = dev_get_priv(dev); - struct udevice *disp_dev; - int err; - - err = uclass_first_device_err(UCLASS_DISPLAY, &disp_dev); - if (err) - return err; - - priv->display = disp_dev; - - err = display_read_timing(disp_dev, timings); - if (err) - return err; - -#endif - return 0; -} - -static int malidp_probe(struct udevice *dev) -{ - struct video_priv *uc_priv = dev_get_uclass_priv(dev); - struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); - ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer"); - struct malidp_priv *priv = dev_get_priv(dev); - struct display_timing timings; - phys_addr_t fb_base, fb_size; - const char *format; - u32 value; - int err; - - if (!ofnode_valid(framebuffer)) - return -EINVAL; - - err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk); - if (err) { - dev_err(dev, "failed to get pixel clock\n"); - return err; - } - err = clk_get_by_name(dev, "aclk", &priv->aclk); - if (err) { - dev_err(dev, "failed to get AXI clock\n"); - goto fail_aclk; - } - - err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings); - if (err) { - dev_err(dev, "failed to get any display timings\n"); - goto fail_timings; - } - - err = malidp_update_timings_from_edid(dev, &timings); - if (err) { - printf("malidp_update_timings_from_edid failed: %d\n", err); - goto fail_timings; - } - - fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size); - if (fb_base != FDT_ADDR_T_NONE) { - uc_plat->base = fb_base; - uc_plat->size = fb_size; - } else { - printf("cannot get address size for framebuffer\n"); - } - - err = ofnode_read_u32(framebuffer, "width", &value); - if (err) - goto fail_timings; - uc_priv->xsize = (ushort)value; - - err = ofnode_read_u32(framebuffer, "height", &value); - if (err) - goto fail_timings; - uc_priv->ysize = (ushort)value; - - format = ofnode_read_string(framebuffer, "format"); - if (!format) { - err = -EINVAL; - goto fail_timings; - } else if (!strncmp(format, "a8r8g8b8", 8)) { - uc_priv->bpix = VIDEO_BPP32; - } - - uc_priv->rot = 0; - priv->base_addr = (phys_addr_t)dev_read_addr(dev); - - clk_enable(&priv->pxlclk); - clk_enable(&priv->aclk); - - value = malidp_get_hwid(priv->base_addr); - printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value), - (value >> 12) & 0xf, (value >> 8) & 0xf); - - if (MALIDP_PRODUCT_ID(value) == MALIDP500) { - /* DP500 is special */ - priv->modeset_regs_offset = 0x28; - priv->dc_status_addr = priv->base_addr; - priv->dc_control_addr = priv->base_addr + 0xc; - priv->cval_addr = priv->base_addr + 0xf00; - priv->config_bit_shift = 17; - priv->clear_irq = 0; - } else { - priv->modeset_regs_offset = 0x30; - priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS; - priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL; - priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID; - priv->config_bit_shift = 16; - priv->clear_irq = MALIDP_REG_CLEARIRQ; - } - - /* enter config mode */ - err = malidp_enter_config(priv); - if (err) - return err; - - /* disable interrupts */ - writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ); - writel(0xffffffff, priv->dc_status_addr + priv->clear_irq); - - err = malidp_setup_mode(priv, &timings); - if (err) - return err; - - malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1, - (phys_addr_t)uc_plat->base); - - err = malidp_leave_config(priv); - if (err) - return err; - - malidp_set_configvalid(priv); - - return 0; -} - -static int malidp_bind(struct udevice *dev) -{ - struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); - - /* choose max possible size: 2K x 2K, XRGB888 framebuffer */ - uc_plat->size = 4 * 2048 * 2048; - - return 0; -} - -static const struct udevice_id malidp_ids[] = { - { .compatible = "arm,mali-dp500" }, - { .compatible = "arm,mali-dp550" }, - { .compatible = "arm,mali-dp650" }, - { } -}; - -U_BOOT_DRIVER(mali_dp) = { - .name = "mali_dp", - .id = UCLASS_VIDEO, - .of_match = malidp_ids, - .bind = malidp_bind, - .probe = malidp_probe, - .priv_auto = sizeof(struct malidp_priv), - .ops = &malidp_ops, -}; From 68735fd33427ff1576f37391f24b5d8912afe45e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 12 Nov 2025 14:00:03 -0600 Subject: [PATCH 2/7] video: tegra: Rework some of the driver dependencies Looking these drivers over, all of them cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Furthermore, update the logic a bit more to reflect which parts are optional when other drivers are enabled and which parts cannot be enabled (meaningfully) by themselves. Reviewed-by: Svyatoslav Ryhel Signed-off-by: Tom Rini --- configs/star_defconfig | 1 + drivers/video/tegra/Kconfig | 19 ++++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/configs/star_defconfig b/configs/star_defconfig index 59eabdcb2b4..7015c417e9e 100644 --- a/configs/star_defconfig +++ b/configs/star_defconfig @@ -86,4 +86,5 @@ CONFIG_VIDEO_LCD_LG_LH400WV3=y CONFIG_VIDEO_LCD_HITACHI_TX10D07VM0BAA=y CONFIG_BACKLIGHT_AAT2870=y CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_TEGRA=y CONFIG_TEGRA_8BIT_CPU_BRIDGE=y diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig index f32972d937e..8bc29f2838b 100644 --- a/drivers/video/tegra/Kconfig +++ b/drivers/video/tegra/Kconfig @@ -1,10 +1,12 @@ config HOST1X_TEGRA - bool "NVIDIA Tegra host1x BUS support" - depends on SIMPLE_BUS + bool + select SIMPLE_BUS + help + NVIDIA Tegra host1x BUS support config VIDEO_TEGRA bool "Enable Display Controller support on Tegra devices" - depends on OF_CONTROL + depends on OF_CONTROL && ARCH_TEGRA select HOST1X_TEGRA help Enable support for Display Controller found in Tegra SoC. The @@ -17,7 +19,7 @@ config VIDEO_TEGRA config VIDEO_DSI_TEGRA bool "Enable DSI controller support on Tegra devices" - depends on VIDEO_BRIDGE && PANEL && DM_GPIO + depends on VIDEO_BRIDGE && PANEL && DM_GPIO && ARCH_TEGRA select VIDEO_TEGRA select VIDEO_MIPI_DSI help @@ -27,7 +29,7 @@ config VIDEO_DSI_TEGRA config VIDEO_HDMI_TEGRA bool "Enable HDMI support on Tegra devices" - depends on VIDEO_BRIDGE && DM_I2C + depends on VIDEO_BRIDGE && DM_I2C && ARCH_TEGRA select I2C_EDID select VIDEO_TEGRA help @@ -36,16 +38,14 @@ config VIDEO_HDMI_TEGRA config TEGRA_BACKLIGHT_PWM bool "Enable Tegra DC PWM backlight support" - depends on BACKLIGHT - select VIDEO_TEGRA + depends on BACKLIGHT && VIDEO_TEGRA help Enable support for the Display Controller dependent PWM backlight found in the Tegra SoC and usually used with DSI panels. config TEGRA_8BIT_CPU_BRIDGE bool "Enable 8 bit panel communication protocol for Tegra 20/30" - depends on VIDEO_BRIDGE && DM_GPIO - select VIDEO_TEGRA + depends on VIDEO_BRIDGE && DM_GPIO && VIDEO_TEGRA select VIDEO_MIPI_DSI help Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control @@ -54,6 +54,7 @@ config TEGRA_8BIT_CPU_BRIDGE config VIDEO_TEGRA124 bool "Enable video support on Tegra124" + depends on ARCH_TEGRA imply VIDEO_DAMAGE help Tegra124 supports many video output options including eDP and From 96d1e8b29b4fc3aa150bce520f33966955efa456 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 12 Nov 2025 14:00:04 -0600 Subject: [PATCH 3/7] video: Tighten some video driver dependencies A few video drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini --- drivers/video/Kconfig | 4 ++++ drivers/video/bridge/Kconfig | 2 +- drivers/video/exynos/Kconfig | 2 +- drivers/video/imx/Kconfig | 1 + drivers/video/meson/Kconfig | 2 +- drivers/video/rockchip/Kconfig | 2 +- drivers/video/stm32/Kconfig | 1 - drivers/video/ti/Kconfig | 1 + 8 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index a12df55f84f..0fc1c161541 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -523,6 +523,7 @@ config ATMEL_LCD_BGR555 config VIDEO_BCM2835 bool "Display support for BCM2835" + depends on ARCH_BCM283X imply VIDEO_DAMAGE help The graphics processor already sets up the display so this driver @@ -755,6 +756,7 @@ source "drivers/video/meson/Kconfig" config VIDEO_MVEBU bool "Armada XP LCD controller" + depends on ARCH_MVEBU imply VIDEO_DAMAGE ---help--- Support for the LCD controller integrated in the Marvell @@ -796,6 +798,7 @@ config NXP_TDA19988 config ATMEL_HLCD bool "Enable ATMEL video support using HLCDC" + depends on ARCH_AT91 imply VIDEO_DAMAGE help HLCDC supports video output to an attached LCD panel. @@ -907,6 +910,7 @@ source "drivers/video/imx/Kconfig" config VIDEO_MXS bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs" + depends on MACH_IMX imply VIDEO_DAMAGE help Enable framebuffer driver for i.MX28/i.MX6UL/i.MX7 processors diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index a48cec7a138..5322a002928 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -53,7 +53,7 @@ config VIDEO_BRIDGE_SOLOMON_SSD2825 config VIDEO_BRIDGE_TOSHIBA_TC358768 bool "Support Toshiba TC358768 MIPI DSI bridge" - depends on VIDEO_BRIDGE && PANEL && DM_GPIO + depends on VIDEO_BRIDGE && PANEL && DM_GPIO && !64BIT select VIDEO_MIPI_DSI select DM_I2C help diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig index a2cf752aac0..1fffec5c9c5 100644 --- a/drivers/video/exynos/Kconfig +++ b/drivers/video/exynos/Kconfig @@ -1,7 +1,7 @@ menuconfig VIDEO_EXYNOS bool "Enable Exynos video support" - depends on VIDEO + depends on VIDEO && ARCH_EXYNOS help Enable support for various video output options on Exynos SoCs. diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index 4a1927c66d7..b35ba965efc 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -23,3 +23,4 @@ config IMX_LDB config IMX_LCDIF bool "i.MX LCDIFv3 LCD controller" + depends on MACH_IMX diff --git a/drivers/video/meson/Kconfig b/drivers/video/meson/Kconfig index fcf486ca0a3..77c3017382e 100644 --- a/drivers/video/meson/Kconfig +++ b/drivers/video/meson/Kconfig @@ -6,7 +6,7 @@ config VIDEO_MESON bool "Enable Amlogic Meson video support" - depends on VIDEO + depends on VIDEO && ARCH_MESON select DISPLAY imply VIDEO_DAMAGE help diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 0f4550a29e3..96af6d28ef0 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -10,7 +10,7 @@ menuconfig VIDEO_ROCKCHIP bool "Enable Rockchip Video Support" - depends on VIDEO + depends on VIDEO && ARCH_ROCKCHIP imply VIDEO_DAMAGE help Rockchip SoCs provide video output capabilities for High-Definition diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig index c354c402c28..ea4ce6799fd 100644 --- a/drivers/video/stm32/Kconfig +++ b/drivers/video/stm32/Kconfig @@ -7,7 +7,6 @@ menuconfig VIDEO_STM32 bool "Enable STM32 video support" - depends on VIDEO imply VIDEO_DAMAGE help STM32 supports many video output options including RGB and diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig index 3081e9e8c09..0483f760ea1 100644 --- a/drivers/video/ti/Kconfig +++ b/drivers/video/ti/Kconfig @@ -4,5 +4,6 @@ # config AM335X_LCD bool "Enable AM335x video support" + depends on ARCH_OMAP2PLUS help Supports video output to an attached LCD panel. From e1bcce1dbbb13a7ec1e8f02e8ce27fad8c550f23 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 12 Nov 2025 14:00:05 -0600 Subject: [PATCH 4/7] video: anx9804: Only build when needed The logic for how to handle this video driver is slightly odd. Only in the case of when CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 is enabled do we need to have this file built, and otherwise we have a dummy function in use. Correct the logic by only building this file when needed. Signed-off-by: Tom Rini --- drivers/video/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 4189b81ba6b..984768ea156 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -56,7 +56,7 @@ obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_VIDEO_EFI) += efi.o obj-y += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o -obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o +obj-$(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX10D07VM0BAA) += hitachi-tx10d07vm0baa.o From 082e5118dab3a23c3d61ed429ad03195efe57653 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 12 Nov 2025 14:00:06 -0600 Subject: [PATCH 5/7] video: ihs_video_out: Add missing to ihs_video_out.c This driver references IO macros while relying on an indirection inclusion of . Add the missing include directly. Signed-off-by: Tom Rini --- drivers/video/ihs_video_out.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/ihs_video_out.c b/drivers/video/ihs_video_out.c index bf4d4995c36..e2130274b49 100644 --- a/drivers/video/ihs_video_out.c +++ b/drivers/video/ihs_video_out.c @@ -15,6 +15,7 @@ #include #include #include +#include static const uint MAX_X_CHARS = 53; static const uint MAX_Y_CHARS = 26; From 5d3af86ae16f1207e1b38b00fccb5d01965cc778 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 12 Nov 2025 14:00:07 -0600 Subject: [PATCH 6/7] video: sharp-lq101r1sx01: Do not make use of 'z' for printing non-size_t The debug macros in this driver make use of the z prefix when printing regular, non-size_t variables and this results in a warning. Drop 'z'. Signed-off-by: Tom Rini --- drivers/video/sharp-lq101r1sx01.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c index 4fdf0da8a94..1c7cef777c3 100644 --- a/drivers/video/sharp-lq101r1sx01.c +++ b/drivers/video/sharp-lq101r1sx01.c @@ -40,14 +40,14 @@ static int sharp_lq101r1sx01_write(struct mipi_dsi_device *dsi, ret = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); if (ret < 0) { - log_debug("%s: failed to write %02x to %04x: %zd\n", + log_debug("%s: failed to write %02x to %04x: %d\n", __func__, value, offset, ret); return ret; } ret = mipi_dsi_dcs_nop(dsi); if (ret < 0) { - log_debug("%s: failed to send DCS nop: %zd\n", + log_debug("%s: failed to send DCS nop: %d\n", __func__, ret); return ret; } From b6f78b815af652cf7ce47db48f93d6283cad4c5b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 12 Nov 2025 14:00:08 -0600 Subject: [PATCH 7/7] video: stm32: stm32_ltdc: Add missing to stm32_ltdc.c This driver references the SZ_ macros while relying on an indirection inclusion of . Add the missing include directly. Signed-off-by: Tom Rini --- drivers/video/stm32/stm32_ltdc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 0a062c8939d..1281acaaade 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -20,6 +20,7 @@ #include #include #include +#include struct stm32_ltdc_priv { void __iomem *regs;