diff --git a/.b4-config b/.b4-config new file mode 100644 index 00000000000..6ba10cf9b50 --- /dev/null +++ b/.b4-config @@ -0,0 +1,7 @@ +# Configuration for the `b4` tool +# See https://b4.docs.kernel.org/en/latest/config.html + +[b4] + send-series-to = u-boot@lists.denx.de + send-auto-to-cmd = echo "" + send-auto-cc-cmd = scripts/get_maintainer.pl diff --git a/.gitattributes b/.gitattributes index 735b13da278..7a7c4163560 100644 --- a/.gitattributes +++ b/.gitattributes @@ -6,4 +6,3 @@ *.ttf binary *.gz binary *.png binary -*.svg binary diff --git a/COPYING b/COPYING new file mode 120000 index 00000000000..1ed3ba6a13c --- /dev/null +++ b/COPYING @@ -0,0 +1 @@ +Licenses/gpl-2.0.txt \ No newline at end of file diff --git a/MAINTAINERS b/MAINTAINERS index b030242a2d8..12043a1f82e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -346,7 +346,6 @@ F: drivers/spi/gxp_spi.c ARM IPQ40XX M: Robert Marko -M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ F: include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -1226,7 +1225,7 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-freebsd.git FREESCALE QORIQ -M: Priyanka Jain +M: Peng Fan S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git F: drivers/watchdog/sp805_wdt.c @@ -1294,6 +1293,11 @@ T: git git://github.com/ARM-software/u-boot.git F: drivers/video/mali_dp.c F: drivers/i2c/i2c-versatile.c +MBEDTLS +M: Raymond Mao +S: Maintained +F: lib/mbedtls/ + MEMBUF M: Simon Glass S: Maintained @@ -1408,10 +1412,12 @@ M: Jaehoon Chung S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git F: drivers/mmc/ +N: mmc NETWORK M: Joe Hershberger M: Ramon Fried +M: Jerome Forissier S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-net.git F: drivers/net/ @@ -1421,6 +1427,7 @@ F: net/ NETWORK (LWIP) M: Jerome Forissier S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-net.git F: cmd/lwip/ F: cmd/net-lwip.c F: configs/qemu_arm64_lwip_defconfig @@ -1513,6 +1520,7 @@ F: test/cmd/pci_mps.c POWER M: Jaehoon Chung +M: Peng Fan S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-pmic.git F: drivers/power/ diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 402f0bec173..d51a9e2ff7f 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -209,7 +209,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; @@ -220,7 +220,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index 2ab143e38f8..886cc89fdb6 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -87,6 +87,10 @@ disable-over-current; }; +&usb31 { + status = "okay"; +}; + &watchdog0 { status = "okay"; }; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index eb82d663204..ea80d1bed15 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -232,6 +232,18 @@ status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index e6d8fe6a907..864f4093ef8 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -137,3 +137,7 @@ &usb0 { status = "okay"; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 85ec0e6937e..cebed7397d4 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -386,12 +386,14 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - *(u64 *)to = __raw_readq(from); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } } } @@ -416,12 +418,14 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - __raw_writeq(*(u64 *)from, to); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } } } diff --git a/arch/arm/mach-renesas/cpu_info-rzg2l.c b/arch/arm/mach-renesas/cpu_info-rzg2l.c index ab95ce76388..a9cb9f72dd3 100644 --- a/arch/arm/mach-renesas/cpu_info-rzg2l.c +++ b/arch/arm/mach-renesas/cpu_info-rzg2l.c @@ -30,7 +30,7 @@ static const struct tfa_info *get_tfa_info(void) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) { + if (atf_fdt_blob && fdt_magic(atf_fdt_blob) == FDT_MAGIC) { unsigned int i; for (i = 0; i < ARRAY_SIZE(tfa_info); i++) { if (!fdt_node_check_compatible(atf_fdt_blob, 0, diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 9ef82cf46c0..b8f2f73e283 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -98,6 +98,8 @@ #define SOC64_HANDOFF_IOCTL_LEN 96 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_FPGA_LEN 42 +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_FPGA_LEN 44 #else #define SOC64_HANDOFF_FPGA_LEN 40 #endif diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 2099c51b682..1a461de4819 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -398,10 +398,8 @@ int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len); int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len); int mbox_init(void); -#ifdef CONFIG_CADENCE_QSPI int mbox_qspi_close(void); int mbox_qspi_open(void); -#endif int mbox_reset_cold(void); int mbox_hps_stage_notify(u32 execution_stage); diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 054a28d845d..f768a3a55cb 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 #define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C #define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0 0x1F0 #define SYSMGR_SOC64_MPFE_CONFIG 0x228 #define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 #define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) + +/* + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0 + * Bits[14:13] Port Overcurrent + * Bit[12] Reset Pulse Override + */ +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR GENMASK(14, 13) +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR BIT(12) +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR 1 +/* BIT 1 actually reflects PIPE power present signal */ +#define SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1 2 #else #define SYSMGR_SOC64_NAND_AXUSER 0x5c #define SYSMGR_SOC64_DMA_L3MASTER 0x74 diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index c442af02888..7e0f3875b7c 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -214,10 +214,7 @@ int qspi_flash_software_reset(void) /* Get the flash info */ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, - CONFIG_SF_DEFAULT_MODE, &flash); - if (ret) { debug("Failed to initialize SPI flash at "); debug("%u:%u (error %d)\n", CONFIG_SF_DEFAULT_BUS, diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index b212a94b321..a531030f5be 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -57,6 +57,7 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, resp, ARRAY_SIZE(resp)); if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) { + invalidate_dcache_range((uintptr_t)resp_buf, (uintptr_t)(resp_buf + *resp_buf_len)); if (!resp[0]) *resp_buf_len = resp[1]; } diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 4b42158be9d..913f93c8f94 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -8,9 +8,29 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +/* + * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse + * generation and setting PORT_OVERCURRENT bit so that until we turn on the + * Vbus, it doesn't give false information about Vbus to the HPS controller. + */ +static void sysmgr_config_usb3(void) +{ + u32 reg_val = 0; + + reg_val = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR, + SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR, + SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1); + writel(reg_val, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); +} +#endif + /* * Configure all the pin muxes */ @@ -18,6 +38,10 @@ void sysmgr_pinmux_init(void) { populate_sysmgr_pinmux(); populate_sysmgr_fpgaintf_module(); + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + sysmgr_config_usb3(); +#endif } /* diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS index 55e485faa96..15660cd17d4 100644 --- a/board/Marvell/mvebu_armada-8k/MAINTAINERS +++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS @@ -13,7 +13,6 @@ F: configs/mvebu_mcbin-88f8040_defconfig Puzzle-M801 BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/mvebu_puzzle-m801-88f8040_defconfig F: arch/arm/dts/armada-8040-puzzle-m801.dts diff --git a/board/iomega/iconnect/MAINTAINERS b/board/iomega/iconnect/MAINTAINERS index a1b018e8169..d9093b28ef0 100644 --- a/board/iomega/iconnect/MAINTAINERS +++ b/board/iomega/iconnect/MAINTAINERS @@ -1,6 +1,5 @@ ICONNECT BOARD M: Tony Dinh -M: Luka Perkov S: Maintained F: board/iomega/iconnect/ F: include/configs/iconnect.h diff --git a/board/mikrotik/crs3xx-98dx3236/MAINTAINERS b/board/mikrotik/crs3xx-98dx3236/MAINTAINERS index 906ff98970b..04423556924 100644 --- a/board/mikrotik/crs3xx-98dx3236/MAINTAINERS +++ b/board/mikrotik/crs3xx-98dx3236/MAINTAINERS @@ -1,13 +1,11 @@ CRS3XX-98DX3236 BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: board/mikrotik/crs3xx-98dx3236/ F: include/configs/crs3xx-98dx3236.h CRS305-1G-4S BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/crs305-1g-4s_defconfig F: configs/crs305-1g-4s-bit_defconfig @@ -16,7 +14,6 @@ F: arch/arm/dts/armada-xp-crs305-1g-4s-bit.dts CRS326-24G-2S BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/crs326-24g-2s_defconfig F: configs/crs326-24g-2s-bit_defconfig @@ -25,7 +22,6 @@ F: arch/arm/dts/armada-xp-crs326-24g-2s-bit.dts CRS328-4C-20S-4S BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/crs328-4c-20s-4s_defconfig F: configs/crs328-4c-20s-4s-bit_defconfig diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 4d7c9b9f80f..136f4486eb0 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -309,7 +309,7 @@ static int phytec_get_product_name(struct phytec_eeprom_data *data, som_type = 1; break; default: - pr_err("%s: Invalid SOM type: %i", __func__, api2->som_type); + pr_err("%s: Invalid SOM type: %i\n", __func__, api2->som_type); return -EINVAL; }; diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 006a817d0e2..eeb7cd6899a 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -6,7 +6,7 @@ fdtaddr=0x88000000 loadaddr=0x82000000 -scriptaddr=0x80000000 +scriptaddr=0x89100000 fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 006a817d0e2..eeb7cd6899a 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -6,7 +6,7 @@ fdtaddr=0x88000000 loadaddr=0x82000000 -scriptaddr=0x80000000 +scriptaddr=0x89100000 fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index bf251c4bcdd..67d2b87f144 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -5,7 +5,7 @@ fdtaddr=0x88000000 loadaddr=0x82000000 -scriptaddr=0x80000000 +scriptaddr=0x89100000 fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c index 509c5dbb156..3c8f8d04cbd 100644 --- a/board/renesas/rzg2l/rzg2l.c +++ b/board/renesas/rzg2l/rzg2l.c @@ -22,7 +22,7 @@ int board_fit_config_name_match(const char *name) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - if (fdt_magic(atf_fdt_blob) != FDT_MAGIC) + if (!atf_fdt_blob || fdt_magic(atf_fdt_blob) != FDT_MAGIC) return -1; if (is_rzg2l_board("renesas,r9a07g044l2")) @@ -36,7 +36,7 @@ static void apply_atf_overlay(void *fdt_blob) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + if (atf_fdt_blob && fdt_magic(atf_fdt_blob) == FDT_MAGIC) fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0); } diff --git a/board/zyxel/nsa310s/MAINTAINERS b/board/zyxel/nsa310s/MAINTAINERS index 11106acf3e9..865c98f7724 100644 --- a/board/zyxel/nsa310s/MAINTAINERS +++ b/board/zyxel/nsa310s/MAINTAINERS @@ -1,6 +1,5 @@ NSA310S BOARD M: Tony Dinh -M: Luka Perkov S: Maintained F: board/zyxel/nsa310s/ F: include/configs/nsa310s.h diff --git a/common/memsize.c b/common/memsize.c index 86109579c95..3c3ae6f1eba 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -52,7 +52,10 @@ long get_ram_size(long *base, long maxsize) long val; long size; int i = 0; - int dcache_en = dcache_status(); + int dcache_en = 0; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + dcache_en = dcache_status(); for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index b373201dbaa..9ca1910d53f 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x9ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex5" CONFIG_SPL_FS_FAT=y @@ -45,6 +46,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x9fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SPL_MTD=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_SPI_FLASH_MTD=y @@ -101,7 +103,10 @@ CONFIG_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000 CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 1c3664bc0d7..44c12db08b5 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_MTD=y CONFIG_SPL_SPI_FLASH_MTD=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index edce692ecd1..4607dc73343 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -1,93 +1,3 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_ARCH_SOCFPGA=y -CONFIG_TEXT_BASE=0x200000 -CONFIG_SYS_MALLOC_LEN=0x500000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -CONFIG_SF_DEFAULT_MODE=0x2003 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x200 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="intel/socfpga_agilex_socdk" -CONFIG_DM_RESET=y -CONFIG_SPL_STACK=0xffe3f000 -CONFIG_SPL_TEXT_BASE=0xFFE00000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_SYS_LOAD_ADDR=0x02000000 +#include + CONFIG_SOCFPGA_SECURE_VAB_AUTH=y -CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex" -CONFIG_SPL_FS_FAT=y -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 -CONFIG_BOOTDELAY=5 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="earlycon" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" -CONFIG_SYS_PBSIZE=2082 -CONFIG_SPL_MAX_SIZE=0x40000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_HAVE_INIT_STACK=y -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 -CONFIG_SPL_CACHE=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_UPSTREAM=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SPL_ALTERA_SDRAM=y -CONFIG_DWAPB_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_DW=y -CONFIG_SYS_MMC_MAX_BLK_COUNT=256 -CONFIG_MMC_DW=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_MII=y -CONFIG_SYS_NS16550_MEM32=y -CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y -CONFIG_USB=y -CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y -CONFIG_DESIGNWARE_WATCHDOG=y -CONFIG_WDT=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y -CONFIG_SPL_CRC32=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 879556614f6..d501fcddf3d 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 5d51c4786c0..a4798e2f953 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x3ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SOCFPGA_SECURE_VAB_AUTH=y CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 90134d8f3f3..fe191d09714 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" diff --git a/doc/README.commands.itest b/doc/README.commands.itest deleted file mode 100644 index 5e0fe86247a..00000000000 --- a/doc/README.commands.itest +++ /dev/null @@ -1,16 +0,0 @@ -A slow day today so here is a revised itest command with provisional -support for comparing strings as well :-)) - -Now table driven to allow the operators --eq, -ne, -lt, -gt, -le, -ge, ==, !=, <>, <, >, <=, >= - -Uses the expected command modifier for integer compares of width 1, 2 or -4 bytes of .b, .w, .l and the new modifer of .s for a string compare. -String comparison is over the length of the shorter, this hopefully -avoids missing terminators when using an indirect pointer. - -eg. -if itest.l *40000 == 12345678 then; .... -if itest.w *40000 != 1234 then; .... -if itest.b *40000 >= 12 then; .... -if itest.s *40000 -eq hello then; .... diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst index 34a75e7fb00..90b4ddf387b 100644 --- a/doc/arch/nios2.rst +++ b/doc/arch/nios2.rst @@ -13,7 +13,7 @@ Please refer to the link for Linux port and toolchains: http://rocketboards.org/foswiki/view/Documentation/NiosIILinuxUserManual The Nios II port of u-boot is controlled by device tree. Please check -out doc/README.fdt-control. +out :doc:`/develop/devicetree/control`. To add a new board/configuration (eg, mysystem) to u-boot, you will need three files. diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst index 7a3125d705b..40e144948a3 100644 --- a/doc/board/ti/am335x_evm.rst +++ b/doc/board/ti/am335x_evm.rst @@ -354,6 +354,16 @@ first. Falcon Mode: FAT SD cards ------------------------- +Compile with additional changes in config variables in menuconfig: + +:: + + CONFIG_SPL_LEGACY_IMAGE_FORMAT=y # to support non-FIT images + CONFIG_LEGACY_IMAGE_FORMAT=y # if commented then SPL Legacy support stops + # CONFIG_SPL_ENV_IS_NOWHERE is not set + CONFIG_SPL_ENV_IS_IN_FAT=y + + In this case the additional file is written to the filesystem. In this example we assume that the uImage and device tree to be used are already on the FAT filesystem (only the uImage MUST be for this to function diff --git a/doc/build/documentation.rst b/doc/build/documentation.rst index 098c96a4c4f..b55a4666643 100644 --- a/doc/build/documentation.rst +++ b/doc/build/documentation.rst @@ -16,6 +16,9 @@ the following dependencies are needed to build the documentation: * texinfo (if building the `Infodoc documentation`_) +When submitting patches for documentation always build with KDOC_WERROR=1 to +treat warnings as errors. + HTML documentation ------------------ diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index 0233945f8b6..8811e1d5c23 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -282,7 +282,7 @@ U-Boot can be divided into three phases: TPL, SPL and U-Boot proper. The full devicetree is available to U-Boot proper, but normally only a subset (or none at all) is available to TPL and SPL. See 'Pre-Relocation Support' and -'SPL Support' in doc/driver-model/design.rst for more details. +'SPL Support' in :doc:`/develop/driver-model/design` for more details. Using several DTBs in the SPL (SPL_MULTI_DTB_FIT Kconfig option) diff --git a/doc/develop/driver-model/ethernet.rst b/doc/develop/driver-model/ethernet.rst index 73c3a728dbf..2e1df744d4a 100644 --- a/doc/develop/driver-model/ethernet.rst +++ b/doc/develop/driver-model/ethernet.rst @@ -8,7 +8,7 @@ own ethernet device driver. Here we will describe a new pseudo 'APE' driver. Most existing drivers do already - and new network driver MUST - use the U-Boot core driver model. Generic information about this can be found in -doc/driver-model/design.rst, this document will thus focus on the network +:doc:`/develop/driver-model/design`, this document will thus focus on the network specific code parts. Some drivers are still using the old Ethernet interface, differences between the two and hints about porting will be handled at the end. diff --git a/doc/develop/pics/spl_after_reloc.svg b/doc/develop/pics/spl_after_reloc.svg index 93e3d599526..052ae3fcc8f 100644 --- a/doc/develop/pics/spl_after_reloc.svg +++ b/doc/develop/pics/spl_after_reloc.svg @@ -1,4 +1,293 @@ - - - -
Heap (simple_malloc)
Global Data
Stack
0x0
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN
gd->malloc_base
gd, gd->start_addr_sp
CONFIG_SPL_STACK_R_ADDR
DRAM SPL after relocation
SPL BSS
CONFIG_SPL_BSS_MAX_SIZE
CONFIG_SPL_BSS_START_ADDR
 \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + DRAM SPL after relocation + + + Heap (simple_malloc) + Global Data + Stack + SPL BSS + + + + + + + gd, gd->start_addr_sp + CONFIG_SPL_STACK_R_ADDR + CONFIG_SPL_BSS_START_ADDR + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN + 0x0 + + + gd->malloc_base + + + CONFIG_SPL_BSS_MAX_SIZE + + + diff --git a/doc/develop/pics/spl_before_reloc.svg b/doc/develop/pics/spl_before_reloc.svg index e69de29bb2d..7b967097ff9 100644 --- a/doc/develop/pics/spl_before_reloc.svg +++ b/doc/develop/pics/spl_before_reloc.svg @@ -0,0 +1,386 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ready RAM (SRAM, locked cache etc.) SPL before relocation + + + Stack + Global Data + Heap + SPL BSS + + + + + + + + + + gd, gd->start_addr_sp + gd->malloc_base + CONFIG_SPL_STACK orCONFIG_SYS_INIT_SP_ADDR + CONFIG_SPL_BSS_START_ADDR + CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK + 0x0 + + + + + CONFIG_SYS_MALLOC_F_LEN + CONFIG_SPL_BSS_MAX_SIZE + + + diff --git a/doc/develop/process.rst b/doc/develop/process.rst index 0c6fb31e87b..4bfbf0eb9c6 100644 --- a/doc/develop/process.rst +++ b/doc/develop/process.rst @@ -139,7 +139,9 @@ comments). Even a "I have no time now, will look into it later" message is better than nothing. Also, if there are remarks to a patch, these should leave no doubt if they were just comments and the patch will be accepted anyway, or if the patch should be -reworked/resubmitted, or if it was rejected. +reworked/resubmitted, or if it was rejected. However, if a submitter +feels it has been too long since posting their patch and not received +any feedback, it is OK to follow-up and ask. Review Process, Git Tags ------------------------ diff --git a/doc/develop/spl.rst b/doc/develop/spl.rst index 7f2eac50806..08b51172014 100644 --- a/doc/develop/spl.rst +++ b/doc/develop/spl.rst @@ -145,7 +145,7 @@ fdtgrep is also used to remove: 'bootph-verify' (VPL)) All the nodes remaining in the SPL devicetree are bound -(see doc/driver-model/design.rst). +(see :doc:`/develop/driver-model/design`). NOTE: U-Boot migrated to a new schema for the u-boot,dm-* tags in 2023. Please update to use the new bootph-* tags as described in the diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 77197d79380..3764f65c221 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -99,9 +99,6 @@ For this particular issue you can use ``DEFAULT_DEVICE_TREE`` instead:: There is no general way to remove quotes. -If CONFIG_ENV_SOURCE_FILE is empty and the default filename is not present, then -the old-style C environment is used instead. See below. - Old-style C environment ----------------------- @@ -114,6 +111,9 @@ Board maintainers are encouraged to migrate to the text-based environment as it is easier to maintain. The distro-board script still requires the old-style environments, so use :doc:`/develop/bootstd/index` instead. +If both the text-based environment file and the old-style C environment are +defined, the variables from the old-style C environment will override those set +in the text-based environment file. List of environment variables ----------------------------- diff --git a/doc/usage/fit/overlay-fdt-boot.rst b/doc/usage/fit/overlay-fdt-boot.rst index 3d7296ad913..d687e98ea2a 100644 --- a/doc/usage/fit/overlay-fdt-boot.rst +++ b/doc/usage/fit/overlay-fdt-boot.rst @@ -13,7 +13,7 @@ that matches the desired configuration. This document focuses on specifically using overlays as part of a FIT image. General information regarding overlays including its syntax and building it -can be found in doc/README.fdt-overlays +can be found in :doc:`/usage/fdt_overlays` Configuration without overlays ------------------------------ diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 242740a4b00..fdbf834bb2f 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -22,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; struct socfpga_clk_plat { void __iomem *regs; + int pllgrp; + int bitmask; }; /* @@ -544,14 +547,11 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) /* Get EMAC clock source */ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); if (emac_id == AGILEX_EMAC0_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK, ctl); else if (emac_id == AGILEX_EMAC1_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK, ctl); else if (emac_id == AGILEX_EMAC2_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK, ctl); else return 0; @@ -643,8 +643,125 @@ static ulong socfpga_clk_get_rate(struct clk *clk) } } +static int bitmask_from_clk_id(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + + switch (clk->id) { + case AGILEX_MPU_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK; + break; + case AGILEX_L4_MAIN_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK; + break; + case AGILEX_L4_MP_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK; + break; + case AGILEX_L4_SP_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK; + break; + case AGILEX_CS_AT_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_TRACE_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_PDBG_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_TIMER_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK; + break; + case AGILEX_S2F_USER0_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK; + break; + case AGILEX_EMAC0_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK; + break; + case AGILEX_EMAC1_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK; + break; + case AGILEX_EMAC2_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK; + break; + case AGILEX_EMAC_PTP_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK; + break; + case AGILEX_GPIO_DB_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK; + break; + case AGILEX_SDMMC_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK; + break; + case AGILEX_S2F_USER1_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK; + break; + case AGILEX_PSI_REF_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK; + break; + case AGILEX_USB_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK; + break; + case AGILEX_SPI_M_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK; + break; + case AGILEX_NAND_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK; + break; + default: + return -ENXIO; + } + + return 0; +} + static int socfpga_clk_enable(struct clk *clk) { + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + uintptr_t base_addr = (uintptr_t)plat->regs; + int ret; + + ret = bitmask_from_clk_id(clk); + if (ret) + return ret; + + setbits_le32(base_addr + plat->pllgrp, plat->bitmask); + + return 0; +} + +static int socfpga_clk_disable(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + uintptr_t base_addr = (uintptr_t)plat->regs; + int ret; + + ret = bitmask_from_clk_id(clk); + if (ret) + return ret; + + clrbits_le32(base_addr + plat->pllgrp, plat->bitmask); + return 0; } @@ -672,6 +789,7 @@ static int socfpga_clk_of_to_plat(struct udevice *dev) static struct clk_ops socfpga_clk_ops = { .enable = socfpga_clk_enable, + .disable = socfpga_clk_disable, .get_rate = socfpga_clk_get_rate, }; diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h index b3e8841a512..be639957940 100644 --- a/drivers/clk/altera/clk-agilex.h +++ b/drivers/clk/altera/clk-agilex.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2025 Altera Corporation */ #ifndef _CLK_AGILEX_ @@ -210,7 +211,26 @@ struct cm_config { #define CLKMGR_LOSTLOCK_SET_MASK BIT(0) +#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0) +#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1) +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) +#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3) +#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4) +#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5) +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6) + +#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0) +#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1) +#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2) +#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3) +#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4) #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6) +#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7) +#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8) +#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9) +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10) + #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index 21f94959a04..2a2f86a650e 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -38,6 +38,8 @@ #define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n) #define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) #define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n) +#define IOSSM_MAILBOX_SPEC_VERSION_MASK GENMASK(2, 0) +#define IOSSM_MAILBOX_SPEC_VERSION(n) FIELD_GET(IOSSM_MAILBOX_SPEC_VERSION_MASK, n) /* Offset of Mailbox Read-only Registers */ #define IOSSM_MAILBOX_HEADER_OFFSET 0x0 @@ -383,6 +385,23 @@ err: return ret; } +static bool is_mailbox_spec_compatible(struct io96b_info *io96b_ctrl) +{ + u32 mailbox_header; + u8 mailbox_spec_ver; + + mailbox_header = readl(io96b_ctrl->io96b[0].io96b_csr_addr + + IOSSM_MAILBOX_HEADER_OFFSET); + mailbox_spec_ver = IOSSM_MAILBOX_SPEC_VERSION(mailbox_header); + printf("%s: IOSSM mailbox version: %d\n", __func__, mailbox_spec_ver); + + /* for now there are two mailbox spec versions, 0 and 1; only version 1 is compatible */ + if (!mailbox_spec_ver) + return false; + + return true; +} + /* * Initial function to be called to set memory interface IP type and instance ID * IP type and instance ID need to be determined before sending mailbox command @@ -392,6 +411,11 @@ void io96b_mb_init(struct io96b_info *io96b_ctrl) int i, j; u32 mem_intf_info_0, mem_intf_info_1; + if (!is_mailbox_spec_compatible(io96b_ctrl)) { + printf("DDR: Failed to get compatible mailbox version\n"); + hang(); + } + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); for (i = 0; i < io96b_ctrl->num_instance; i++) { diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index f8fc92060db..2d0093c591c 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: Triggerring emif reset\n"); hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); - /* if seq2core[3] = 0, we are good */ + /* if seq2core[2:0] = 0b0000_0111, we are good */ ret = wait_for_bit_le32((const void *)(plat->hmc + RSTHANDSHAKESTAT), - DDR_HMC_SEQ2CORE_INT_RESP_MASK, - false, 1000, false); + DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK, + true, 1000, false); if (ret) { printf("DDR: failed to get ack from EMIF\n"); return ret; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6031cef560e..6fe0653922c 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -77,7 +77,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) #define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0x0000000f -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) +#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK GENMASK(2, 0) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f #define DDR_HMC_ERRINTEN_INTMASK \ diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index a54976e7889..8ad716f410e 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -764,7 +764,7 @@ int designware_i2c_of_to_plat(struct udevice *bus) ret = reset_get_bulk(bus, &priv->resets); if (ret) { - if (ret != -ENOTSUPP) + if (ret != -ENOTSUPP && ret != -ENOENT) dev_warn(bus, "Can't get reset: %d\n", ret); } else { reset_deassert_bulk(&priv->resets); diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 3b86bc9b18c..db4e0129c2e 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -29,7 +29,9 @@ struct socfpga_dwmci_plat { /* socfpga implmentation specific driver private data */ struct dwmci_socfpga_priv_data { + struct udevice *dev; struct dwmci_host host; + struct clk mmc_clk_ciu; unsigned int drvsel; unsigned int smplsel; }; @@ -51,28 +53,23 @@ static void socfpga_dwmci_reset(struct udevice *dev) static int socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; + int ret; + u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); - /* Get clock manager base address */ - struct udevice *clkmgr_dev; - int ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@ffd10000", &clkmgr_dev); - + ret = clk_get_by_name(priv->dev, "ciu", &priv->mmc_clk_ciu); if (ret) { - printf("Failed to get clkmgr device: %d\n", ret); + debug("%s: Failed to get SDMMC clock from dts\n", __func__); return ret; } - fdt_addr_t clkmgr_base = dev_read_addr(clkmgr_dev); - - if (clkmgr_base == FDT_ADDR_T_NONE) { - printf("Failed to read base address from clkmgr DT node\n"); - return -EINVAL; - } - /* Disable SDMMC clock. */ - clrbits_le32(clkmgr_base + CLKMGR_PERPLL_EN, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + ret = clk_disable(&priv->mmc_clk_ciu); + if (ret) { + printf("%s: Failed to disable SDMMC clock\n", __func__); + return ret; + } debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); @@ -92,8 +89,11 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) #endif /* Enable SDMMC clock */ - setbits_le32(clkmgr_base + CLKMGR_PERPLL_EN, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + ret = clk_enable(&priv->mmc_clk_ciu); + if (ret) { + printf("%s: Failed to enable SDMMC clock\n", __func__); + return ret; + } return 0; } @@ -169,6 +169,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + priv->dev = dev; int ret; ret = socfpga_dwmmc_get_clk_rate(dev); diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 4b50f351d35..a77206d3815 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -212,6 +212,8 @@ void nand_init(void) if (nand_chip.select_chip) nand_chip.select_chip(mtd, 0); + mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; + /* NAND chip may require reset after power-on */ nand_command(0, 0, 0, NAND_CMD_RESET); } diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index 41f0d958447..1f41ce28b0b 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -243,7 +243,7 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable clrbits_le32(rcar->app_base + PCIERSTCTRL1, APP_HOLD_PHY_RST); - ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, !(val & BIT(18)), 10000); + ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, val & BIT(18), 10000); if (ret < 0) return ret; @@ -306,6 +306,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar) if (ret) goto err_unprepare; + mdelay(1); + setbits_le32(rcar->app_base + PCIEMSR0, DEVICE_TYPE_RC | ((rcar->num_lanes < 4) ? BIFUR_MOD_SET_ON : 0)); @@ -314,6 +316,9 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar) if (ret) goto err_unprepare; + reset_status(&rcar->pwr_rst); + mdelay(1); + rcar_gen4_pcie_additional_common_init(rcar); return 0; diff --git a/dts/Makefile b/dts/Makefile index 86bf8dc2156..fd4ae31a533 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2011 The Chromium OS Authors. # This Makefile builds the internal U-Boot fdt if CONFIG_OF_CONTROL is -# enabled. See doc/README.fdt-control for more details. +# enabled. See doc/develop/devicetree/control.rst for more details. DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%) ifeq ($(DEVICE_TREE),) diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h new file mode 100644 index 00000000000..a6252180516 --- /dev/null +++ b/include/dt-bindings/clock/agilex-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Altera Corporation + */ + +#ifndef __AGILEX_CLOCK_H +#define __AGILEX_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX_OSC1 0 +#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX_CB_INTOSC_LS_CLK 2 +#define AGILEX_L4_SYS_FREE_CLK 3 +#define AGILEX_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX_MAIN_PLL_CLK 5 +#define AGILEX_MAIN_PLL_C0_CLK 6 +#define AGILEX_MAIN_PLL_C1_CLK 7 +#define AGILEX_MAIN_PLL_C2_CLK 8 +#define AGILEX_MAIN_PLL_C3_CLK 9 +#define AGILEX_PERIPH_PLL_CLK 10 +#define AGILEX_PERIPH_PLL_C0_CLK 11 +#define AGILEX_PERIPH_PLL_C1_CLK 12 +#define AGILEX_PERIPH_PLL_C2_CLK 13 +#define AGILEX_PERIPH_PLL_C3_CLK 14 +#define AGILEX_MPU_FREE_CLK 15 +#define AGILEX_MPU_CCU_CLK 16 +#define AGILEX_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX_L3_MAIN_FREE_CLK 18 +#define AGILEX_NOC_FREE_CLK 19 +#define AGILEX_S2F_USR0_CLK 20 +#define AGILEX_NOC_CLK 21 +#define AGILEX_EMAC_A_FREE_CLK 22 +#define AGILEX_EMAC_B_FREE_CLK 23 +#define AGILEX_EMAC_PTP_FREE_CLK 24 +#define AGILEX_GPIO_DB_FREE_CLK 25 +#define AGILEX_SDMMC_FREE_CLK 26 +#define AGILEX_S2F_USER0_FREE_CLK 27 +#define AGILEX_S2F_USER1_FREE_CLK 28 +#define AGILEX_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX_MPU_CLK 30 +#define AGILEX_MPU_PERIPH_CLK 31 +#define AGILEX_L4_MAIN_CLK 32 +#define AGILEX_L4_MP_CLK 33 +#define AGILEX_L4_SP_CLK 34 +#define AGILEX_CS_AT_CLK 35 +#define AGILEX_CS_TRACE_CLK 36 +#define AGILEX_CS_PDBG_CLK 37 +#define AGILEX_CS_TIMER_CLK 38 +#define AGILEX_S2F_USER0_CLK 39 +#define AGILEX_EMAC0_CLK 40 +#define AGILEX_EMAC1_CLK 41 +#define AGILEX_EMAC2_CLK 42 +#define AGILEX_EMAC_PTP_CLK 43 +#define AGILEX_GPIO_DB_CLK 44 +#define AGILEX_NAND_CLK 45 +#define AGILEX_PSI_REF_CLK 46 +#define AGILEX_S2F_USER1_CLK 47 +#define AGILEX_SDMMC_CLK 48 +#define AGILEX_SPI_M_CLK 49 +#define AGILEX_USB_CLK 50 +#define AGILEX_NAND_X_CLK 51 +#define AGILEX_NAND_ECC_CLK 52 +#define AGILEX_NUM_CLKS 53 + +#endif /* __AGILEX_CLOCK_H */ diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 900113ca3e9..13e44be1d06 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -123,22 +123,6 @@ config EFI_VARIABLE_FILE_STORE Select this option if you want non-volatile UEFI variables to be stored as file /ubootefi.var on the EFI system partition. -config EFI_RT_VOLATILE_STORE - bool "Allow variable runtime services in volatile storage (e.g RAM)" - depends on EFI_VARIABLE_FILE_STORE - help - When EFI variables are stored on file we don't allow SetVariableRT, - since the OS doesn't know how to write that file. At the same time - we copy runtime variables in DRAM and support GetVariableRT - - Enable this option to allow SetVariableRT on the RAM backend of - the EFI variable storage. The OS will be responsible for syncing - the RAM contents to the file, otherwise any changes made during - runtime won't persist reboots. - Authenticated variables are not supported. Note that this will - violate the EFI spec since writing auth variables will return - EFI_INVALID_PARAMETER - config EFI_MM_COMM_TEE bool "UEFI variables storage service via the trusted world" depends on OPTEE @@ -157,6 +141,31 @@ config EFI_MM_COMM_TEE MM buffer. The data is copied by u-boot to the shared buffer before issuing the door bell event. +config EFI_VARIABLE_NO_STORE + bool "Don't persist non-volatile UEFI variables" + help + If you choose this option, non-volatile variables cannot be persisted. + You could still provide non-volatile variables via + EFI_VARIABLES_PRESEED. + +endchoice + +config EFI_RT_VOLATILE_STORE + bool "Allow variable runtime services in volatile storage (e.g RAM)" + depends on EFI_VARIABLE_FILE_STORE + help + When EFI variables are stored on file we don't allow SetVariableRT, + since the OS doesn't know how to write that file. At the same time + we copy runtime variables in DRAM and support GetVariableRT + + Enable this option to allow SetVariableRT on the RAM backend of + the EFI variable storage. The OS will be responsible for syncing + the RAM contents to the file, otherwise any changes made during + runtime won't persist reboots. + Authenticated variables are not supported. Note that this will + violate the EFI spec since writing auth variables will return + EFI_INVALID_PARAMETER + config FFA_SHARED_MM_BUF_SIZE int "Memory size of the shared MM communication buffer" depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT @@ -184,15 +193,6 @@ config FFA_SHARED_MM_BUF_ADDR the MM SP in secure world. It is assumed that the MM SP knows the address of the shared MM communication buffer. -config EFI_VARIABLE_NO_STORE - bool "Don't persist non-volatile UEFI variables" - help - If you choose this option, non-volatile variables cannot be persisted. - You could still provide non-volatile variables via - EFI_VARIABLES_PRESEED. - -endchoice - config EFI_VARIABLES_PRESEED bool "Initial values for UEFI variables" depends on !COMPILE_TEST