imx8ulp_evk: Switch to use devicetree imported from Linux kernel release
Enable OF_UPSTREAM for i.MX8ULP EVK so that devicetree imported from Linux kernel release can be used. If mailbox@29220000 is enabled, gd->arch.ele_dev will be set to this device for communication with ELE firmware. This is incorrect because mu@27020000 is the MU used for communication with the ELE firmware. To prevent misconfiguration, disable mailbox@29220000. The driver model for watchdog timer is not enabled yet, so disable wdog3 temporarily. Signed-off-by: Alice Guo <alice.guo@nxp.com>
This commit is contained in:
Alice Guo
@@ -881,9 +881,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \
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fsl-imx8qxp-mek.dtb \
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imx8-capricorn-cxg3.dtb \
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dtb-$(CONFIG_ARCH_IMX8ULP) += \
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imx8ulp-evk.dtb
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dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-data-modul-edm-sbc.dtb \
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imx8mm-icore-mx8mm-ctouch2.dtb \
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@@ -22,6 +22,14 @@
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bootph-all;
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};
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&mu {
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status = "disabled";
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};
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&wdog3 {
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status = "disabled";
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};
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&per_bridge4 {
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bootph-pre-ram;
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};
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@@ -1,125 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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/dts-v1/;
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#include "imx8ulp.dtsi"
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/ {
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model = "NXP i.MX8ULP EVK";
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compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
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chosen {
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stdout-path = &lpuart5;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>;
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};
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clock_ext_rmii: clock-ext-rmii {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "ext_rmii_clk";
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#clock-cells = <0>;
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};
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clock_ext_ts: clock-ext-ts {
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compatible = "fixed-clock";
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/* External ts clock is 50MHZ from PHY on EVK board. */
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clock-frequency = <50000000>;
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clock-output-names = "ext_ts_clk";
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#clock-cells = <0>;
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};
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};
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&lpuart5 {
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/* console */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpuart5>;
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pinctrl-1 = <&pinctrl_lpuart5>;
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status = "okay";
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};
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&usdhc0 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-1 = <&pinctrl_enet>;
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clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
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<&pcc4 IMX8ULP_CLK_ENET>,
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<&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
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<&clock_ext_rmii>;
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clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
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assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
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assigned-clock-parents = <&clock_ext_ts>;
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phy-mode = "rmii";
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phy-handle = <ðphy>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <1>;
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};
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};
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};
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&iomuxc1 {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX8ULP_PAD_PTE15__ENET0_MDC 0x43
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MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
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MX8ULP_PAD_PTE17__ENET0_RXER 0x43
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MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
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MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
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MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
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MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
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MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
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MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
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MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
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MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
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>;
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};
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins = <
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MX8ULP_PAD_PTF14__LPUART5_TX 0x3
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MX8ULP_PAD_PTF15__LPUART5_RX 0x3
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
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MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
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MX8ULP_PAD_PTD10__SDHC0_D0 0x43
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MX8ULP_PAD_PTD9__SDHC0_D1 0x43
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MX8ULP_PAD_PTD8__SDHC0_D2 0x43
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MX8ULP_PAD_PTD7__SDHC0_D3 0x43
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MX8ULP_PAD_PTD6__SDHC0_D4 0x43
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MX8ULP_PAD_PTD5__SDHC0_D5 0x43
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MX8ULP_PAD_PTD4__SDHC0_D6 0x43
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MX8ULP_PAD_PTD3__SDHC0_D7 0x43
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MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
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>;
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};
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};
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&wdog3 {
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status = "disabled";
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};
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@@ -1,476 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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#include <dt-bindings/clock/imx8ulp-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/imx8ulp-power.h>
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#include "imx8ulp-pinfunc.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec;
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gpio0 = &gpiod;
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gpio1 = &gpioe;
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gpio2 = &gpiof;
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mmc0 = &usdhc0;
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mmc1 = &usdhc1;
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mmc2 = &usdhc2;
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serial0 = &lpuart4;
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serial1 = &lpuart5;
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serial2 = &lpuart6;
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serial3 = &lpuart7;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A35_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_L2: l2-cache0 {
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compatible = "cache";
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};
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};
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gic: interrupt-controller@2d400000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
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<0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-affinity = <&A35_0>, <&A35_1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
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};
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frosc: clock-frosc {
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compatible = "fixed-clock";
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clock-frequency = <192000000>;
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clock-output-names = "frosc";
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#clock-cells = <0>;
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};
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lposc: clock-lposc {
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compatible = "fixed-clock";
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clock-frequency = <1000000>;
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clock-output-names = "lposc";
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#clock-cells = <0>;
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};
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rosc: clock-rosc {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "rosc";
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#clock-cells = <0>;
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};
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sosc: clock-sosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "sosc";
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#clock-cells = <0>;
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};
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sram@2201f000 {
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compatible = "mmio-sram";
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reg = <0x0 0x2201f000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x2201f000 0x1000>;
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scmi_buf: scmi-sram-section@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x400>;
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};
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};
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firmware {
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scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0xc20000fe>;
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#address-cells = <1>;
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#size-cells = <0>;
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shmem = <&scmi_buf>;
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scmi_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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scmi_sensor: protocol@15 {
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reg = <0x15>;
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#thermal-sensor-cells = <1>;
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};
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>;
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s4muap: mailbox@27020000 {
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compatible = "fsl,imx8ulp-mu-s4";
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reg = <0x27020000 0x10000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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per_bridge3: bus@29000000 {
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compatible = "simple-bus";
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reg = <0x29000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mu: mailbox@29220000 {
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compatible = "fsl,imx8ulp-mu";
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reg = <0x29220000 0x10000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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mu3: mailbox@29230000 {
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compatible = "fsl,imx8ulp-mu";
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reg = <0x29230000 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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wdog3: watchdog@292a0000 {
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compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
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reg = <0x292a0000 0x10000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
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assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
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timeout-sec = <40>;
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};
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cgc1: clock-controller@292c0000 {
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compatible = "fsl,imx8ulp-cgc1";
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reg = <0x292c0000 0x10000>;
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#clock-cells = <1>;
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};
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pcc3: clock-controller@292d0000 {
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compatible = "fsl,imx8ulp-pcc3";
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reg = <0x292d0000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tpm5: tpm@29340000 {
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compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
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reg = <0x29340000 0x1000>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
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<&pcc3 IMX8ULP_CLK_TPM5>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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lpi2c4: i2c@29370000 {
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compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x29370000 0x10000>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
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<&pcc3 IMX8ULP_CLK_LPI2C4>;
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clock-names = "per", "ipg";
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpi2c5: i2c@29380000 {
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compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x29380000 0x10000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
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<&pcc3 IMX8ULP_CLK_LPI2C5>;
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clock-names = "per", "ipg";
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpuart4: serial@29390000 {
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compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x29390000 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart5: serial@293a0000 {
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compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x293a0000 0x1000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpspi4: spi@293b0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
|
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reg = <0x293b0000 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
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<&pcc3 IMX8ULP_CLK_LPSPI4>;
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clock-names = "per", "ipg";
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
|
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};
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lpspi5: spi@293c0000 {
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#address-cells = <1>;
|
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#size-cells = <0>;
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compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
|
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reg = <0x293c0000 0x10000>;
|
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
|
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<&pcc3 IMX8ULP_CLK_LPSPI5>;
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clock-names = "per", "ipg";
|
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
|
||||
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
per_bridge4: bus@29800000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x29800000 0x800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pcc4: clock-controller@29800000 {
|
||||
compatible = "fsl,imx8ulp-pcc4";
|
||||
reg = <0x29800000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
lpi2c6: i2c@29840000 {
|
||||
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x29840000 0x10000>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
|
||||
<&pcc4 IMX8ULP_CLK_LPI2C6>;
|
||||
clock-names = "per", "ipg";
|
||||
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
|
||||
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c7: i2c@29850000 {
|
||||
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x29850000 0x10000>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
|
||||
<&pcc4 IMX8ULP_CLK_LPI2C7>;
|
||||
clock-names = "per", "ipg";
|
||||
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
|
||||
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart6: serial@29860000 {
|
||||
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x29860000 0x1000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart7: serial@29870000 {
|
||||
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x29870000 0x1000>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc1: pinctrl@298c0000 {
|
||||
compatible = "fsl,imx8ulp-iomuxc1";
|
||||
reg = <0x298c0000 0x10000>;
|
||||
};
|
||||
|
||||
usdhc0: mmc@298d0000 {
|
||||
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x298d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
|
||||
<&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
|
||||
<&pcc4 IMX8ULP_CLK_USDHC0>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: mmc@298e0000 {
|
||||
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x298e0000 0x10000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
|
||||
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
|
||||
<&pcc4 IMX8ULP_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@298f0000 {
|
||||
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x298f0000 0x10000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
|
||||
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
|
||||
<&pcc4 IMX8ULP_CLK_USDHC2>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec: ethernet@29950000 {
|
||||
compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
|
||||
reg = <0x29950000 0x10000>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0";
|
||||
fsl,num-tx-queues = <1>;
|
||||
fsl,num-rx-queues = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpioe: gpio@2d000080 {
|
||||
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
|
||||
<&pcc4 IMX8ULP_CLK_PCTLE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 32 24>;
|
||||
};
|
||||
|
||||
gpiof: gpio@2d010080 {
|
||||
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
|
||||
<&pcc4 IMX8ULP_CLK_PCTLF>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 64 32>;
|
||||
};
|
||||
|
||||
per_bridge5: bus@2d800000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x2d800000 0x800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
cgc2: clock-controller@2da60000 {
|
||||
compatible = "fsl,imx8ulp-cgc2";
|
||||
reg = <0x2da60000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pcc5: clock-controller@2da70000 {
|
||||
compatible = "fsl,imx8ulp-pcc5";
|
||||
reg = <0x2da70000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpiod: gpio@2e200080 {
|
||||
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
|
||||
<&pcc5 IMX8ULP_CLK_RGPIOD>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 0 24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -27,6 +27,7 @@ config TARGET_IMX8ULP_EVK
|
||||
select IMX8ULP
|
||||
select SUPPORT_SPL
|
||||
select IMX8ULP_DRAM
|
||||
imply OF_UPSTREAM
|
||||
|
||||
endchoice
|
||||
|
||||
|
||||
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx8ulp/imximage.cfg"
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8ulp-evk"
|
||||
CONFIG_TARGET_IMX8ULP_EVK=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
CONFIG_SPL_SERIAL=y
|
||||
|
||||
Reference in New Issue
Block a user