6b743f66d8
U-Boot SPL should be executed from LMB BRAM, where its text and data sections are located, while the heap and stack are allocated in DDR memory. Because on the MB-V platform, after power-up, reset, or FPGA load, execution begins from LMB BRAM at address 0x0. Therefore, the SPL binary must be placed in BRAM to support this boot flow. Without it, the system can only be booted via JTAG. A 64KB LMB BRAM region is allocated for U-Boot SPL, starting at address 0x0. This region contains the SPL's text, data, and device tree blob (DTB) sections. The .bss section is placed separately at address 0xF000. _________________0xFFFF |BSS | |_______________|0xF000 |DTB | |_______________| |Data | |_______________| |Text | |_______________|0x0000 A 2MB region of DDR memory is allocated for U-Boot SPL, with the heap starting at address 0x80000000 and the stack at 0x80200000. _________________0xBFFFFFFF |Full U-Boot | |_______________|0x80400000 |Load FIT Image | |_______________|0x80200000 |Stack | |_______________| |Heap | |_______________|0x80000000 Since LMB BRAM is a limited resource with a practical size constraint of 64KB - it cannot accommodate all runtime data. Therefore, the heap and stack are placed at the beginning of DDR memory to ensure sufficient space for SPL execution. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ed4a3618875869287b87b6b57fd55f4c6a36f046.1765206211.git.michal.simek@amd.com
49 lines
1.3 KiB
Plaintext
49 lines
1.3 KiB
Plaintext
CONFIG_RISCV=y
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CONFIG_SYS_MALLOC_LEN=0xe00000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
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CONFIG_SPL_STACK=0x80200000
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CONFIG_SPL_TEXT_BASE=0x0
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CONFIG_SPL_BSS_START_ADDR=0xf000
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CONFIG_SPL_BSS_MAX_SIZE=0x1000
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CONFIG_SYS_BOOTM_LEN=0x800000
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CONFIG_SYS_LOAD_ADDR=0x80200000
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CONFIG_SPL_SIZE_LIMIT=0x10000
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CONFIG_SPL=y
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CONFIG_SYS_CLK_FREQ=100000000
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CONFIG_BOOT_SCRIPT_OFFSET=0x0
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CONFIG_TARGET_XILINX_MBV=y
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# CONFIG_RISCV_ISA_F is not set
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# CONFIG_SPL_SMP is not set
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CONFIG_REMAKE_ELF=y
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CONFIG_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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# CONFIG_BOARD_INIT is not set
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# CONFIG_BOARD_LATE_INIT is not set
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CONFIG_SPL_MAX_SIZE=0xf000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_HAVE_INIT_STACK=y
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
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CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
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CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
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# CONFIG_CMD_MII is not set
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CONFIG_CMD_SNTP=y
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CONFIG_CMD_TIMER=y
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CONFIG_ENV_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DM_MTD=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_EMULATION=y
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CONFIG_XILINX_UARTLITE=y
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CONFIG_XILINX_TIMER=y
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# CONFIG_BINMAN_FDT is not set
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CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
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CONFIG_PANIC_HANG=y
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