05240d541a
This patch cleans the vendor code of DDR initialization up, converts the driver to fit in DM framework and use a firmware[1] packaged by binman to ship PHY configuration. Currently the driver is only capable of initializing the controller to work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants of LicheePi 4A boards and I could test with. Support for other configurations could be easily added later. Link: https://github.com/ziyao233/th1520-firmware # [1] Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
37 lines
975 B
Makefile
37 lines
975 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2015 Google, Inc
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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obj-$(CONFIG_$(PHASE_)DM) += ram-uclass.o
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obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o
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obj-$(CONFIG_SANDBOX) += sandbox_ram.o
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obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/
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obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
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obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ASPEED_RAM) += aspeed/
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obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
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obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
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obj-$(CONFIG_RAM_SIFIVE) += sifive/
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ifdef CONFIG_XPL_BUILD
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obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
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endif
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obj-$(CONFIG_DRAM_SUN20I_D1) += sunxi/
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obj-$(CONFIG_ARCH_OCTEON) += octeon/
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obj-$(CONFIG_ARCH_RENESAS) += renesas/
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obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
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ifdef CONFIG_XPL_BUILD
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obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += thead/
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endif
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