a51b7dfc6f
Configure RMMI and M-PHY registers for HS mode required for selection of bit rate series A or B. If it is not a calibrated part, then switch back to SLOWAUTO_MODE and skip all these configurations. Implemented below sequence as per the DWC RMMI databook. 1. Override RMMI CBRATESEL with the desired rate. 2. Set TX_CFGUPDT_0 to 1'b1 for one TX_CFGCLK_0 cycle. 3. Override PHY rx_req to 1, then poll on PHY rx_ack register till it goes 1(both lanes). 4. Override PHY rx_req to 0, then poll on PHY rx_ack register till it goes 0(both lanes). 5. Remove PHY rx_req override(both lanes). 6. Start the LS PMC. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250724044402.260149-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* UFS Host driver for Synopsys Designware Core
|
|
*
|
|
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* Authors: Joao Pinto <jpinto@synopsys.com>
|
|
*/
|
|
|
|
#ifndef _UFSHCD_DWC_H
|
|
#define _UFSHCD_DWC_H
|
|
|
|
/* PHY modes */
|
|
#define UFSHCD_DWC_PHY_MODE_ROM 0
|
|
|
|
/* RMMI Attributes */
|
|
#define CBREFCLKCTRL2 0x8132
|
|
#define CBCRCTRL 0x811F
|
|
#define CBC10DIRECTCONF2 0x810E
|
|
#define CBRATESEL 0x8114
|
|
#define CBCREGADDRLSB 0x8116
|
|
#define CBCREGADDRMSB 0x8117
|
|
#define CBCREGWRLSB 0x8118
|
|
#define CBCREGWRMSB 0x8119
|
|
#define CBCREGRDLSB 0x811A
|
|
#define CBCREGRDMSB 0x811B
|
|
#define CBCREGRDWRSEL 0x811C
|
|
|
|
#define CBREFREFCLK_GATE_OVR_EN BIT(7)
|
|
|
|
/* M-PHY Attributes */
|
|
#define MTX_FSM_STATE 0x41
|
|
#define MRX_FSM_STATE 0xC1
|
|
|
|
/* M-PHY registers */
|
|
#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100))
|
|
#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100))
|
|
#define FAST_FLAGS(n) (0x401C + ((n) * 0x100))
|
|
#define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100))
|
|
#define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100))
|
|
#define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100))
|
|
|
|
/* Tx/Rx FSM state */
|
|
enum rx_fsm_state {
|
|
RX_STATE_DISABLED = 0,
|
|
RX_STATE_HIBERN8 = 1,
|
|
RX_STATE_SLEEP = 2,
|
|
RX_STATE_STALL = 3,
|
|
RX_STATE_LSBURST = 4,
|
|
RX_STATE_HSBURST = 5,
|
|
};
|
|
|
|
enum tx_fsm_state {
|
|
TX_STATE_DISABLED = 0,
|
|
TX_STATE_HIBERN8 = 1,
|
|
TX_STATE_SLEEP = 2,
|
|
TX_STATE_STALL = 3,
|
|
TX_STATE_LSBURST = 4,
|
|
TX_STATE_HSBURST = 5,
|
|
};
|
|
|
|
struct ufshcd_dme_attr_val {
|
|
u32 attr_sel;
|
|
u32 mib_val;
|
|
u8 peer;
|
|
};
|
|
|
|
int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
|
|
enum ufs_notify_change_status status);
|
|
int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
|
|
const struct ufshcd_dme_attr_val *v, int n);
|
|
#endif /* End of Header */
|