b546189a4b
Add initial device trees for Renesas R-Car X5H R8A78000 SoC. Include very basic clock, reset, power domain headers which are used to control supported peripherals via SCMI / SCP. The headers are currently kept limited to avoid possible ABI break. A lot of clock are still stubbed via fixed-clock, this is going to be gradually removed over time, as more of the platform is upstreamed. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*
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* IDs match SCP 4.27
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*/
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#ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
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#define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
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/*
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* These definition indices match the Clock ID defined by SCP FW 4.27.
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*/
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#define SCP_CLOCK_ID_MDLC_UFS0 202
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#define SCP_CLOCK_ID_MDLC_UFS1 203
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#define SCP_CLOCK_ID_MDLC_SDHI0 204
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#define SCP_CLOCK_ID_MDLC_XPCS0 316
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#define SCP_CLOCK_ID_MDLC_XPCS1 317
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#define SCP_CLOCK_ID_MDLC_XPCS2 318
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#define SCP_CLOCK_ID_MDLC_XPCS3 319
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#define SCP_CLOCK_ID_MDLC_XPCS4 320
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#define SCP_CLOCK_ID_MDLC_XPCS5 321
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#define SCP_CLOCK_ID_MDLC_XPCS6 322
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#define SCP_CLOCK_ID_MDLC_XPCS7 323
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#define SCP_CLOCK_ID_MDLC_RSW3 324
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#define SCP_CLOCK_ID_MDLC_RSW3TSN 325
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#define SCP_CLOCK_ID_MDLC_RSW3AES 326
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES0 327
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES1 328
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES2 329
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES3 330
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES4 331
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES5 332
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES6 333
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#define SCP_CLOCK_ID_MDLC_RSW3TSNTES7 334
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#define SCP_CLOCK_ID_MDLC_RSW3MFWD 335
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#define SCP_CLOCK_ID_MDLC_MPPHY01 344
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#define SCP_CLOCK_ID_MDLC_MPPHY11 345
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#define SCP_CLOCK_ID_MDLC_MPPHY21 346
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#define SCP_CLOCK_ID_MDLC_MPPHY31 347
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#define SCP_CLOCK_ID_MDLC_MPPHY02 348
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#endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */
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