1817467e48
Add support for imx6ulz_smm_m2d, based on the M2 architecture. Signed-off-by: Andrea Calabrese <andrea.calabrese@amarulasolutions.com>
123 lines
5.3 KiB
C
123 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include "spl_mtypes.h"
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static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = {
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/* IOMUX */
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/* DDR IO TYPE: */
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{0x020E04B4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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{0x020E04AC, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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/* CLOCK: */
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{0x020E027C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
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/* Control: */
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{0x020E0250, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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{0x020E024C, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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{0x020E0490, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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{0x020E0288, 0x000C0030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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{0x020E0270, 0x00000000}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured */
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/* using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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{0x020E0260, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
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{0x020E0264, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
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{0x020E04A0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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/* Data Strobes: */
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{0x020E0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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{0x020E0280, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
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{0x020E0284, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
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/* Data: */
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{0x020E04B0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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{0x020E0498, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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{0x020E04A4, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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{0x020E0244, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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{0x020E0248, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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/* ============================================================================= */
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/* DDR Controller Registers */
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/* ============================================================================= */
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/* Manufacturer:WINBOND */
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/* Device Part Number:W632GU6RB-11 */
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/* Clock Freq.: 400MHz */
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/* Density per CS in Gb: 2 */
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/* Chip Selects used:1 */
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/* Total DRAM density (Gb)2 */
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/* Number of Banks:8 */
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/* Row address: 14 */
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/* Column address: 10 */
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/* Data bus width16 */
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/* ============================================================================= */
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{0x021B001C, 0x00008000}, /* [MMDC_MDSCR] MMDC Core Special Command Register */
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/* ====================================================== */
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/* Calibrations: */
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/* ====================================================== */
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{0x021B0800, 0xA1390003}, /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic */
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/* HW ZQ calibration. */
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{0x021B080C, 0x00070005}, /* [MMDC_MPWLDECTRL0] MMDC PHY Write Leveling Delay Control */
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/* Register 0 */
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{0x021B083C, 0x414C0150}, /* [MMDC_MPDGCTRL0] MMDC PHY Read DQS Gating Control */
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/* Register 0 */
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{0x021B0848, 0x4040383E}, /* [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration */
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/* Register */
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{0x021B0850, 0x40402E2A}, /* [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration */
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/* Register */
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{0x021B081C, 0x33333333}, /* [MMDC_MPRDDQBY0DL] MMDC PHY Read DQ Byte0 Delay Register */
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{0x021B0820, 0x33333333}, /* [MMDC_MPRDDQBY1DL] MMDC PHY Read DQ Byte1 Delay Register */
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{0x021B082C, 0xf3333333}, /* [MMDC_MPWRDQBY0DL] MMDC PHY Write DQ Byte0 Delay Register */
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{0x021B0830, 0xf3333333}, /* [MMDC_MPWRDQBY1DL] MMDC PHY Write DQ Byte1 Delay Register */
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{0x021B08C0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
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/* Complete calibration by forced measurement: */
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{0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
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/* ====================================================== */
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/* MMDC init: */
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/* ====================================================== */
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{0x021B0004, 0x00020024}, /* MMDC0_MDPDC */
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{0x021B0008, 0x1B333030}, /* MMDC0_MDOTC */
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{0x021B000C, 0x3F4352D3}, /* MMDC0_MDCFG0 */
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{0x021B0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */
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{0x021B0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
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{0x021B0018, 0x00201740}, /* MMDC0_MDMISC */
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{0x021B002C, 0x000026D2}, /* MMDC0_MDRWD; recommend to maintain the default values */
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{0x021B0030, 0x00431023}, /* MMDC0_MDOR */
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{0x021B0040, 0x00000047}, /* CS0_END */
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{0x021B0000, 0x83180000}, /* MMDC0_MDCTL */
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/* Mode register writes for CS0 */
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{0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
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{0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
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{0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
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{0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */
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{0x021B001C, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
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/* Mode register writes for CS, commented out automatically */
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/* if only one chip select used */
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/* {0x021B001C, 0x0200803A}, */
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/* {0x021B001C, 0x0000803B}, */
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/* {0x021B001C, 0x00048039}, */
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/* {0x021B001C, 0x15208038}, */
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/* {0x021B001C, 0x04008048}, */
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/* final DDR setup, before operation start: */
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{0x021B0020, 0x00000800}, /* MMDC0_MDREF */
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{0x021B0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
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{0x021B0004, 0x00025564}, /* MMDC0_MDPDC now SDCTL power down enabled */
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{0x021B0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */
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{0x021B001C, 0x00000000}, /* MMDC0_MDSCR, clear this register (especially the */
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/* configuration bit as initialization is complete) */
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};
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struct dram_timing_info bsh_dram_timing_256mb = {
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.ddrc_cfg = ddr_ddrc_cfg_256mb,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb),
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.dram_size = SZ_256M,
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};
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