# Common architecture configuration options

# Copyright (c) 2022, CSIRO.
# SPDX-License-Identifier: Apache-2.0

config SEMIHOST
	bool "Semihosting support for ARM and RISC-V targets"
	depends on ARM || ARM64 || RISCV
	help
	  Semihosting is a mechanism that enables code running on an ARM or
	  RISC-V target to communicate and use the Input/Output facilities on
	  a host computer that is running a debugger.
	  Additional information can be found in:
	  https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
	  https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
	  This option is compatible with hardware and with QEMU, through the
	  (automatic) use of the -semihosting-config switch when invoking it.

config LEGACY_MULTI_LEVEL_TABLE_GENERATION
	bool "Auto generates the multi-level interrupt LUT (deprecated)"
	default y
	select DEPRECATED
	depends on MULTI_LEVEL_INTERRUPTS
	depends on !PLIC
	depends on !NXP_IRQSTEER
	depends on !RV32M1_INTMUX
	depends on !CAVS_ICTL
	depends on !DW_ICTL_ACE
	depends on !DW_ICTL
	help
	  A make-shift Kconfig to continue generating the multi-level interrupt LUT
	  with the legacy way using DT macros.

config ISR_TABLE_SHELL
	bool "Shell command to dump the ISR tables"
	depends on GEN_SW_ISR_TABLE
	depends on SHELL
	help
	  This option enables a shell command to dump the ISR tables.
