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soc: v2: Add st_stm32 structure and common folder

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Add minimum and common structure to start using STM32 on HW model V2.
Duplicated from soc/arm/st_stm32/common with minor modifications:
- common/Kconfig.soc moved to Kconfig as Kconfig.soc should now
be restricted to _SOC_FOO) related symbols
- "depends on LOG_BACKEND_SWO" LOG_BACKEND_SWO_REF_FREQ_HZ instead of if ..
- Symbols depending on series are not present, they'll have to be
introduced when converting respective series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This commit is contained in:
Erwan Gouriou
2024-01-17 15:53:55 +01:00
committed by Jamie McCrae
parent 36b63787a7
commit 0131e1c159
13 changed files with 704 additions and 0 deletions
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5
soc/v2/st_stm32/CMakeLists.txt Normal file
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# Copyright (c) 2024 STMicroelectronics
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(common)
add_subdirectory(${SOC_SERIES})

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soc/v2/st_stm32/Kconfig Normal file
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# Copyright (c) 2024 STMicroelectronics
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_STM32
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
select STM32_ENABLE_DEBUG_SLEEP_STOP if DEBUG || ZTEST
select BUILD_OUTPUT_HEX
rsource "*/Kconfig"
# STM32 wide symbols definitions
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CCM := zephyr,ccm
config STM32_CCM
def_bool $(dt_chosen_enabled,$(DT_CHOSEN_Z_CCM))
config USE_STM32_ASSERT
depends on ASSERT
bool "STM32Cube HAL and LL drivers asserts"
help
Enable asserts in STM32Cube HAL and LL drivers.
config STM32_BACKUP_SRAM
bool "STM32 Backup SRAM"
depends on DT_HAS_ST_STM32_BACKUP_SRAM_ENABLED
help
Enable support for STM32 backup SRAM.
config STM32_ENABLE_DEBUG_SLEEP_STOP
bool "Allow debugger attach in stop/sleep Mode"
help
Some STM32 parts disable the DBGMCU in sleep/stop modes because
of power consumption. As a side-effects this prevents
debuggers from attaching w/o resetting the target. This
effectivly destroys the use-case of `west attach`. Also
SEGGER RTT and similar technologies need this.

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soc/v2/st_stm32/Kconfig.defconfig Normal file
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# ST Microelectronics STM32 all MCU lines
# Copyright (c) 2017, I-SENSE group of ICCS
# SPDX-License-Identifier: Apache-2.0
# Default configurations appplied tp the whole STM32 family
if SOC_FAMILY_STM32
rsource "*/Kconfig.defconfig"
config CORTEX_M_SYSTICK
default n if STM32_LPTIM_TIMER
DT_STM32_RCC_PATH := $(dt_nodelabel_path,rcc)
DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-frequency)
DT_ST_PRESCALER := st,prescaler
DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)"
config LOG_BACKEND_SWO_REF_FREQ_HZ
default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)"
depends on LOG_BACKEND_SWO
# set the tick per sec as a divider of the LPTIM clock source
# with a minimum value of 4096 for SYS_CLOCK_TICKS_PER_SEC to keep
# SYS_CLOCK_TICKS_PER_SEC not too high compared to the LPTIM counter clock
config SYS_CLOCK_TICKS_PER_SEC
default 4096 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16
default 2048 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16
default 1024 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32
default 512 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64
default 256 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128
depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSE
config SYS_CLOCK_TICKS_PER_SEC
default 4000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16
default 2000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16
default 1000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32
default 500 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64
default 250 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128
depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSI
config CLOCK_CONTROL_STM32_CUBE
default y
depends on CLOCK_CONTROL
config CLOCK_CONTROL_INIT_PRIORITY
default 1
depends on CLOCK_CONTROL
config MEMC_STM32
default y
depends on MEMC
endif # SOC_FAMILY_STM32

12
soc/v2/st_stm32/Kconfig.soc Normal file
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# ST Microelectronics STM32 MCU line
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_STM32
bool
config SOC_FAMILY
default "st_stm32" if SOC_FAMILY_STM32
rsource "*/Kconfig.soc"

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soc/v2/st_stm32/common/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
stm32cube_hal.c
soc_config.c
)
zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld)
zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c)
zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld)

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soc/v2/st_stm32/common/ccm.ld Normal file
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/* Copied from linker.ld */
GROUP_START(CCM)
SECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__ccm_start = .;
__ccm_bss_start = .;
*(.ccm_bss)
*(".ccm_bss.*")
__ccm_bss_end = .;
} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
SECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__ccm_noinit_start = .;
*(.ccm_noinit)
*(".ccm_noinit.*")
__ccm_noinit_end = .;
} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
SECTION_PROLOGUE(_CCM_DATA_SECTION_NAME,,SUBALIGN(4))
{
__ccm_data_start = .;
*(.ccm_data)
*(".ccm_data.*")
__ccm_data_end = .;
} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)) AT> ROMABLE_REGION)
__ccm_end = .;
__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);
GROUP_END(CCM)

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soc/v2/st_stm32/common/pinctrl_soc.h Normal file
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/*
* Copyright (c) 2020 Linaro Ltd.
* Copyright (c) 2021 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* STM32 SoC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef CONFIG_SOC_SERIES_STM32F1X
#include <zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h>
#else
#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/** Type for STM32 pin. */
typedef struct pinctrl_soc_pin {
/** Pinmux settings (port, pin and function). */
uint32_t pinmux;
/** Pin configuration (bias, drive and slew rate). */
uint32_t pincfg;
} pinctrl_soc_pin_t;
/**
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
*
* @param node_id Node identifier.
*/
#define Z_PINCTRL_STM32_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
/**
* @brief Definitions used to initialize fields in #pinctrl_pin_t
*/
#define STM32_NO_PULL 0x0
#define STM32_PULL_UP 0x1
#define STM32_PULL_DOWN 0x2
#define STM32_PUSH_PULL 0x0
#define STM32_OPEN_DRAIN 0x1
#define STM32_OUTPUT_LOW 0x0
#define STM32_OUTPUT_HIGH 0x1
#define STM32_GPIO_OUTPUT 0x1
#ifdef CONFIG_SOC_SERIES_STM32F1X
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (F1).
*
* @param node_id Node identifier.
*/
#define Z_PINCTRL_STM32_PINCFG_INIT(node_id) \
(((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPD_SHIFT) | \
((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPD_SHIFT) | \
((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPD_SHIFT) | \
((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_CNF_OUT_0_SHIFT) | \
((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_CNF_OUT_0_SHIFT) | \
((STM32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << STM32_ODR_SHIFT) | \
((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << STM32_MODE_OSPEED_SHIFT))
#else
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (non-F1).
*
* @param node_id Node identifier.
*/
#define Z_PINCTRL_STM32_PINCFG_INIT(node_id) \
(((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPDR_SHIFT) | \
((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPDR_SHIFT) | \
((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPDR_SHIFT) | \
((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_OTYPER_SHIFT) | \
((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_OTYPER_SHIFT) | \
((STM32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << STM32_ODR_SHIFT) | \
((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \
((STM32_GPIO_OUTPUT * DT_PROP(node_id, output_low)) << STM32_MODER_SHIFT) | \
((STM32_GPIO_OUTPUT * DT_PROP(node_id, output_high)) << STM32_MODER_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << STM32_OSPEEDR_SHIFT))
#endif /* CONFIG_SOC_SERIES_STM32F1X */
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param state_prop State property name.
* @param idx State property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
{ .pinmux = Z_PINCTRL_STM32_PINMUX_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)), \
.pincfg = Z_PINCTRL_STM32_PINCFG_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)) },
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_ */

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soc/v2/st_stm32/common/soc_config.c Normal file
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/*
* Copyright (c) 2021 Andrés Manelli <am@toroid.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief System module to support early STM32 MCU configuration
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/arch/cpu.h>
#include <stm32_ll_system.h>
#include <stm32_ll_bus.h>
/**
* @brief Perform SoC configuration at boot.
*
* This should be run early during the boot process but after basic hardware
* initialization is done.
*
* @return 0
*/
static int st_stm32_common_config(void)
{
#ifdef CONFIG_LOG_BACKEND_SWO
/* Enable SWO trace asynchronous mode */
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32H5X)
LL_DBGMCU_EnableTraceClock();
#endif
#if !defined(CONFIG_SOC_SERIES_STM32WBX)
LL_DBGMCU_SetTracePinAssignment(LL_DBGMCU_TRACE_ASYNCH);
#endif
#endif /* CONFIG_LOG_BACKEND_SWO */
#if defined(CONFIG_USE_SEGGER_RTT)
/* On some STM32 boards, for unclear reason,
* RTT feature is working with realtime update only when
* - one of the DMA is clocked.
* See https://github.com/zephyrproject-rtos/zephyr/issues/34324
*/
#if defined(__HAL_RCC_DMA1_CLK_ENABLE)
__HAL_RCC_DMA1_CLK_ENABLE();
#elif defined(__HAL_RCC_GPDMA1_CLK_ENABLE)
__HAL_RCC_GPDMA1_CLK_ENABLE();
#endif /* __HAL_RCC_DMA1_CLK_ENABLE */
/* On some STM32 boards, for unclear reason,
* RTT feature is working with realtime update only when
* - one of the DBGMCU bit STOP/STANDBY/SLEEP is set
* See https://github.com/zephyrproject-rtos/zephyr/issues/34324
*/
#if defined(LL_APB1_GRP1_PERIPH_DBGMCU)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
#elif defined(LL_APB1_GRP2_PERIPH_DBGMCU)
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
#elif defined(LL_APB2_GRP1_PERIPH_DBGMCU)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
#endif /* LL_APB1_GRP1_PERIPH_DBGMCU */
#endif /* CONFIG_USE_SEGGER_RTT */
#if defined(CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP)
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X)
HAL_EnableDBGStopMode();
#else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
#if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
LL_DBGMCU_EnableDBGStopMode();
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
#elif defined(SOC_SERIES_STM32F0X)
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
LL_DBGMCU_EnableDBGStopMode();
LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
#elif defined(SOC_SERIES_STM32L0X)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
LL_DBGMCU_EnableDBGStopMode();
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
#else /* all other parts */
LL_DBGMCU_EnableDBGStopMode();
#endif
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
#else
/* keeping in mind that debugging draws a lot of power we explcitly disable when not needed */
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X)
HAL_DisableDBGStopMode();
#else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
#if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
LL_DBGMCU_DisableDBGStopMode();
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
#elif defined(SOC_SERIES_STM32F0X)
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
LL_DBGMCU_DisableDBGStopMode();
LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
#elif defined(SOC_SERIES_STM32L0X)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
LL_DBGMCU_DisableDBGStopMode();
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
#else /* all other parts */
LL_DBGMCU_DisableDBGStopMode();
#endif
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
#endif /* CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP */
return 0;
}
SYS_INIT(st_stm32_common_config, PRE_KERNEL_1, 1);

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soc/v2/st_stm32/common/stm32_backup_sram.c Normal file
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/*
* Copyright (c) 2021 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_backup_sram
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <stm32_ll_pwr.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(stm32_backup_sram, CONFIG_SOC_LOG_LEVEL);
struct stm32_backup_sram_config {
struct stm32_pclken pclken;
};
static int stm32_backup_sram_init(const struct device *dev)
{
const struct stm32_backup_sram_config *config = dev->config;
int ret;
/* enable clock for subsystem */
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (!device_is_ready(clk)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
ret = clock_control_on(clk, (clock_control_subsys_t)&config->pclken);
if (ret < 0) {
LOG_ERR("Could not initialize backup SRAM clock (%d)", ret);
return ret;
}
/* enable write access to backup domain */
LL_PWR_EnableBkUpAccess();
while (!LL_PWR_IsEnabledBkUpAccess()) {
}
/* enable backup sram regulator (required to retain backup SRAM content
* while in standby or VBAT modes).
*/
LL_PWR_EnableBkUpRegulator();
while (!LL_PWR_IsEnabledBkUpRegulator()) {
}
return 0;
}
static const struct stm32_backup_sram_config config = {
.pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
.enr = DT_INST_CLOCKS_CELL(0, bits) },
};
DEVICE_DT_INST_DEFINE(0, stm32_backup_sram_init, NULL, NULL, &config,
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, NULL);

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soc/v2/st_stm32/common/stm32_backup_sram.ld Normal file
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/*
* Copyright (c) 2021 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
GROUP_START(BACKUP_SRAM)
SECTION_PROLOGUE(_STM32_BACKUP_SRAM_SECTION_NAME, (NOLOAD),)
{
*(.stm32_backup_sram)
*(".stm32_backup_sram.*")
} GROUP_LINK_IN(BACKUP_SRAM)
GROUP_END(BACKUP_SRAM)

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soc/v2/st_stm32/common/stm32_hsem.h Normal file
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/*
* Copyright (c) 2019 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_HSEM_STM32_HSEM_H_
#define ZEPHYR_INCLUDE_DRIVERS_HSEM_STM32_HSEM_H_
#include <soc.h>
#include <stm32_ll_hsem.h>
#include <zephyr/kernel.h>
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE)
/** HW semaphore Complement ID list defined in hw_conf.h from STM32WB
* and used also for H7 dualcore targets
*/
/**
* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or
* erase data in flash. The CPU1 shall not either write or erase in flash when
* this semaphore is taken by the CPU2. When the CPU1 needs to either write or
* erase in flash, it shall first get the semaphore and release it just
* after writing a raw (64bits data) or erasing one sector.
* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and
* CPU2 is using PES bit. By default, CPU2 is using the PES bit to protect its
* timing. The CPU1 may request the CPU2 to use the semaphore instead of the
* PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
*/
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7U
/**
* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or
* erase data in flash. In order to protect its timing, the CPU1 may get this
* semaphore to prevent the CPU2 to either write or erase in flash
* (as this will stall both CPUs)
* The PES bit shall not be used as this may stall the CPU2 in some cases.
*/
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6U
/**
* Index of the semaphore used to manage the CLK48 clock configuration
* When the USB is required, this semaphore shall be taken before configuring
* the CLK48 for USB and should be released after the application switch OFF
* the clock when the USB is not used anymore. When using the RNG, it is good
* enough to use CFG_HW_RNG_SEMID to control CLK48.
* More details in AN5289
*/
#define CFG_HW_CLK48_CONFIG_SEMID 5U
#define CFG_HW_RCC_CRRCR_CCIPR_SEMID CFG_HW_CLK48_CONFIG_SEMID
/* Index of the semaphore used to manage the entry Stop Mode procedure */
#define CFG_HW_ENTRY_STOP_MODE_SEMID 4U
#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1U << CFG_HW_ENTRY_STOP_MODE_SEMID)
/* Index of the semaphore used to access the RCC */
#define CFG_HW_RCC_SEMID 3U
/* Index of the semaphore used to access the FLASH */
#define CFG_HW_FLASH_SEMID 2U
/* Index of the semaphore used to access the PKA */
#define CFG_HW_PKA_SEMID 1U
/* Index of the semaphore used to access the RNG */
#define CFG_HW_RNG_SEMID 0U
/** Index of the semaphore used to access GPIO */
#define CFG_HW_GPIO_SEMID 8U
/** Index of the semaphore used to access the EXTI */
#define CFG_HW_EXTI_SEMID 9U
/** Index of the semaphore for CPU1 mailbox */
#define CFG_HW_IPM_CPU1_SEMID 10U
/** Index of the semaphore for CPU2 mailbox */
#define CFG_HW_IPM_CPU2_SEMID 11U
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
/** HW semaphore from STM32MP1
* EXTI and GPIO are inherited from STM32MP1 Linux.
* Other SEMID are not used by linux and must not be used here,
* but reserved for MPU.
*/
/** Index of the semaphore used to access GPIO */
#define CFG_HW_GPIO_SEMID 0U
/** Index of the semaphore used to access the EXTI */
#define CFG_HW_EXTI_SEMID 1U
#else
/** Fake semaphore ID definition for compilation purpose only */
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 0U
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 0U
#define CFG_HW_CLK48_CONFIG_SEMID 0U
#define CFG_HW_RCC_CRRCR_CCIPR_SEMID 0U
#define CFG_HW_ENTRY_STOP_MODE_SEMID 0U
#define CFG_HW_RCC_SEMID 0U
#define CFG_HW_FLASH_SEMID 0U
#define CFG_HW_PKA_SEMID 0U
#define CFG_HW_RNG_SEMID 0U
#define CFG_HW_GPIO_SEMID 0U
#define CFG_HW_EXTI_SEMID 0U
#define CFG_HW_IPM_CPU1_SEMID 0U
#define CFG_HW_IPM_CPU2_SEMID 0U
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE */
/** Hardware Semaphore wait forever value */
#define HSEM_LOCK_WAIT_FOREVER 0xFFFFFFFFU
/** Hardware Semaphore default retry value */
#define HSEM_LOCK_DEFAULT_RETRY 0x100000U
/**
* @brief Lock Hardware Semaphore
*/
static inline void z_stm32_hsem_lock(uint32_t hsem, uint32_t retry)
{
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \
|| defined(CONFIG_SOC_SERIES_STM32MP1X)
while (LL_HSEM_1StepLock(HSEM, hsem)) {
if (retry != HSEM_LOCK_WAIT_FOREVER) {
retry--;
if (retry == 0) {
k_panic();
}
}
}
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */
}
/**
* @brief Try to lock Hardware Semaphore
*/
static inline int z_stm32_hsem_try_lock(uint32_t hsem)
{
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \
|| defined(CONFIG_SOC_SERIES_STM32MP1X)
if (LL_HSEM_1StepLock(HSEM, hsem)) {
return -EAGAIN;
}
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */
return 0;
}
/**
* @brief Release Hardware Semaphore
*/
static inline void z_stm32_hsem_unlock(uint32_t hsem)
{
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \
|| defined(CONFIG_SOC_SERIES_STM32MP1X)
LL_HSEM_ReleaseLock(HSEM, hsem, 0);
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */
}
/**
* @brief Indicates whether Hardware Semaphore is owned by this core
*/
static inline bool z_stm32_hsem_is_owned(uint32_t hsem)
{
bool owned = false;
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \
|| defined(CONFIG_SOC_SERIES_STM32MP1X)
owned = LL_HSEM_GetCoreId(HSEM, hsem) == LL_HSEM_COREID;
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */
return owned;
}
#endif /* ZEPHYR_INCLUDE_DRIVERS_HSEM_STM32_HSEM_H_ */

53
soc/v2/st_stm32/common/stm32cube_hal.c Normal file
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@@ -0,0 +1,53 @@
/*
* Copyright (c) 2018, I-SENSE group of ICCS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Zephyr's implementation for STM32Cube HAL core initialization
* functions. These functions are declared as __weak in
* STM32Cube HAL in order to be overwritten in case of other
* implementations.
*/
#include <zephyr/kernel.h>
#include <soc.h>
/**
* @brief This function configures the source of stm32cube time base.
* Cube HAL expects a 1ms tick which matches with k_uptime_get_32.
* Tick interrupt priority is not used
* @return HAL status
*/
uint32_t HAL_GetTick(void)
{
return k_uptime_get_32();
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @param Delay: specifies the delay time length, in milliseconds.
* @return None
*/
void HAL_Delay(__IO uint32_t Delay)
{
k_msleep(Delay);
}
#ifdef CONFIG_USE_STM32_ASSERT
/**
* @brief Generates an assert on STM32Cube HAL/LL assert trigger.
* @param file: specifies the file name where assert expression failed.
* @param line: specifies the line number where assert expression failed.
* @return None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* Assert condition have been verified at Cube level, force
* generation here.
*/
__ASSERT(false, "Invalid value line %d @ %s\n", line, file);
}
#endif /* CONFIG_USE_STM32_ASSERT */

2
soc/v2/st_stm32/soc.yml Normal file
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family:
- name: st_stm32