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arch: arm: Add initial support for Cortex-M52 Core

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Add initial support for the Cortex-M52 Core which is an implementation
of the Armv8.1-M mainline architecture.

The support is based on the Cortex-M55 support that already exists in
Zephyr.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
This commit is contained in:
Jisheng Zhang
2025-08-02 06:24:03 +08:00
committed by Johan Hedberg
parent 598eba4d7a
commit 13bdae0ad0
11 changed files with 64 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/core/cortex_m/Kconfig
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@@ -63,6 +63,17 @@ config CPU_CORTEX_M33
help
This option signifies the use of a Cortex-M33 CPU
config CPU_CORTEX_M52
bool
select CPU_CORTEX_M
select ARMV8_1_M_MAINLINE
select ARMV8_M_SE if CPU_HAS_TEE
select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
help
This option signifies the use of a Cortex-M52 CPU
config CPU_CORTEX_M55
bool
select CPU_CORTEX_M

1
arch/arm/core/mpu/arm_mpu.c
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@@ -69,6 +69,7 @@ static uint8_t static_regions_num;
#include "arm_mpu_v7_internal.h"
#elif defined(CONFIG_CPU_CORTEX_M23) || \
defined(CONFIG_CPU_CORTEX_M33) || \
defined(CONFIG_CPU_CORTEX_M52) || \
defined(CONFIG_CPU_CORTEX_M55) || \
defined(CONFIG_CPU_CORTEX_M85) || \
defined(CONFIG_AARCH32_ARMV8_R)

3
arch/arm/core/mpu/arm_mpu_v8_internal.h
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@@ -32,7 +32,8 @@ struct dynamic_region_info {
*/
static struct dynamic_region_info dyn_reg_info[MPU_DYNAMIC_REGION_AREAS_NUM];
#if defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) || \
defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85)
defined(CONFIG_CPU_CORTEX_M52) || defined(CONFIG_CPU_CORTEX_M55) || \
defined(CONFIG_CPU_CORTEX_M85)
static inline void mpu_set_mair0(uint32_t mair0)
{
MPU->MAIR0 = mair0;

10
cmake/gcc-m-cpu.cmake
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@@ -24,6 +24,16 @@ if("${ARCH}" STREQUAL "arm")
else()
set(GCC_M_CPU cortex-m33+nodsp)
endif()
elseif(CONFIG_CPU_CORTEX_M52)
if (CONFIG_ARMV8_1_M_MVEF)
set(GCC_M_CPU cortex-m52)
elseif(CONFIG_ARMV8_1_M_MVEI)
set(GCC_M_CPU cortex-m52+nomve.fp)
elseif(CONFIG_ARMV8_M_DSP)
set(GCC_M_CPU cortex-m52+nomve)
else()
set(GCC_M_CPU cortex-m52+nodsp)
endif()
elseif(CONFIG_CPU_CORTEX_M55)
if (CONFIG_ARMV8_1_M_MVEF)
set(GCC_M_CPU cortex-m55)

4
cmake/gcc-m-fpu.cmake
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@@ -35,6 +35,10 @@ if("${ARCH}" STREQUAL "arm")
set(FPU_FOR_cortex-m7 fpv5-${PRECISION_TOKEN}d16)
set(FPU_FOR_cortex-m33 fpv5-${PRECISION_TOKEN}d16)
set(FPU_FOR_cortex-m33+nodsp fpv5-${PRECISION_TOKEN}d16)
set(FPU_FOR_cortex-m52 auto)
set(FPU_FOR_cortex-m52+nomve.fp auto)
set(FPU_FOR_cortex-m52+nomve auto)
set(FPU_FOR_cortex-m52+nodsp auto)
set(FPU_FOR_cortex-m55 auto)
set(FPU_FOR_cortex-m55+nomve.fp auto)
set(FPU_FOR_cortex-m55+nomve auto)

8
dts/bindings/cpu/arm,cortex-m52.yaml Normal file
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@@ -0,0 +1,8 @@
# Copyright (c) 2025 Synaptics Incorporated
# SPDX-License-Identifier: Apache-2.0
description: ARM Cortex-M52 CPU
compatible: "arm,cortex-m52"
include: arm,cortex-m.yaml

8
dts/bindings/cpu/arm,cortex-m52f.yaml Normal file
View File

@@ -0,0 +1,8 @@
# Copyright (c) 2025 Synaptics Incorporated
# SPDX-License-Identifier: Apache-2.0
description: ARM Cortex-M52F CPU
compatible: "arm,cortex-m52f"
include: arm,cortex-m.yaml

7
include/zephyr/arch/arm/cortex_m/memory_map.h
View File

@@ -67,7 +67,8 @@
#define _PPB_INT_SCS 0xE000E000
#define _PPB_INT_RSVD_2 0xE000F000
#elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) || \
defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85)
defined(CONFIG_CPU_CORTEX_M52) || defined(CONFIG_CPU_CORTEX_M55) || \
defined(CONFIG_CPU_CORTEX_M85)
#define _PPB_INT_RSVD_0 0xE0000000
#define _PPB_INT_SCS 0xE000E000
#define _PPB_INT_SCB 0xE000ED00
@@ -88,8 +89,8 @@
#define _PPB_EXT_PPB 0xE0042000
#define _PPB_EXT_ROM_TABLE 0xE00FF000
#define _PPB_EXT_END_ADDR 0xE00FFFFF
#elif defined(CONFIG_CPU_CORTEX_M33) || defined(CONFIG_CPU_CORTEX_M55) || \
defined(CONFIG_CPU_CORTEX_M85)
#elif defined(CONFIG_CPU_CORTEX_M33) || defined(CONFIG_CPU_CORTEX_M52) || \
defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85)
#undef _PPB_EXT_BASE_ADDR
#define _PPB_EXT_BASE_ADDR 0xE0044000
#define _PPB_EXT_ROM_TABLE 0xE00FF000

4
include/zephyr/arch/arm/mpu/arm_mpu.h
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@@ -10,8 +10,8 @@
defined(CONFIG_CPU_CORTEX_M4) || defined(CONFIG_CPU_CORTEX_M7) || defined(CONFIG_ARMV7_R)
#include <zephyr/arch/arm/mpu/arm_mpu_v7m.h>
#elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) || \
defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85) || \
defined(CONFIG_AARCH32_ARMV8_R)
defined(CONFIG_CPU_CORTEX_M52) || defined(CONFIG_CPU_CORTEX_M55) || \
defined(CONFIG_CPU_CORTEX_M85) || defined(CONFIG_AARCH32_ARMV8_R)
#include <zephyr/arch/arm/mpu/arm_mpu_v8.h>
#else
#error "Unsupported ARM CPU"

4
modules/cmsis_6/cmsis_core_m_defaults.h
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@@ -62,6 +62,8 @@ typedef enum {
#define __CM23_REV 0
#elif defined(CONFIG_CPU_CORTEX_M33)
#define __CM33_REV 0
#elif defined(CONFIG_CPU_CORTEX_M52)
#define __CM52_REV 0
#elif defined(CONFIG_CPU_CORTEX_M55)
#define __CM55_REV 0
#elif defined(CONFIG_CPU_CORTEX_M85)
@@ -135,6 +137,8 @@ typedef enum {
#include <core_cm23.h>
#elif defined(CONFIG_CPU_CORTEX_M33)
#include <core_cm33.h>
#elif defined(CONFIG_CPU_CORTEX_M52)
#include <core_cm52.h>
#elif defined(CONFIG_CPU_CORTEX_M55)
#include <core_cm55.h>
#elif defined(CONFIG_CPU_CORTEX_M85)

10
subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h
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@@ -37,6 +37,16 @@ extern "C" {
#else
#define PROCESSOR_NAME "cortex-m33+nodsp"
#endif
#elif defined(CONFIG_CPU_CORTEX_M52)
#if defined(CONFIG_ARMV8_1_M_MVEF)
#define PROCESSOR_NAME "cortex-m52"
#elif defined(CONFIG_ARMV8_1_M_MVEI)
#define PROCESSOR_NAME "cortex-m52+nomve.fp"
#elif defined(CONFIG_ARMV8_M_DSP)
#define PROCESSOR_NAME "cortex-m52+nomve"
#else
#define PROCESSOR_NAME "cortex-m52+nodsp"
#endif
#elif defined(CONFIG_CPU_CORTEX_M55)
#if defined(CONFIG_ARMV8_1_M_MVEF)
#define PROCESSOR_NAME "cortex-m55"