soc: ti_lm3s6965: Port to HWMv2

Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/ti/lm3s6965/CMakeLists.txt

@@ -13,4 +13,6 @@ zephyr_library_include_directories(
   ${ZEPHYR_BASE}/arch/arm/include
   )
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/ti/lm3s6965/Kconfig

@@ -1,7 +1,7 @@
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_TI_LM3S6965
-	bool "TI LM3S6965"
 	select ARM
 	select CPU_CORTEX_M3
 	select CPU_CORTEX_M_HAS_DWT

soc/ti/lm3s6965/Kconfig.defconfig

@@ -5,9 +5,6 @@
 
 if SOC_TI_LM3S6965
 
-config SOC
-	default "ti_lm3s6965"
-
 config NUM_IRQS
 	# must be >= the highest interrupt number used
 	# - include the UART interrupts and ethernet interrupts

soc/ti/lm3s6965/Kconfig.soc

@@ -1,10 +1,16 @@
-# TI LM3S6965 platform configuration options
-
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
+config SOC_TI_LM3S6965
+	bool
+	help
+	  TI LM3S6965
+
 config SOC_TI_LM3S6965_QEMU
 	def_bool y
 	depends on SOC_TI_LM3S6965
 	# Platform has only been tested on QEMU, not on real hardware, so always
 	# assume it is used for a QEMU target.
+
+config SOC
+	default "ti_lm3s6965" if SOC_TI_LM3S6965

soc/ti/lm3s6965/soc.yml

@@ -0,0 +1,2 @@
+socs:
+- name: ti_lm3s6965