soc: nxp: convert LPC SOC family to hardware model V2

Move LPC family to HWMv2

Signed-off-by: David Leach <david.leach@nxp.com>

soc: nxp: convert LPC SOC family to hardware model V2

Move LPC family to HWMv2

Signed-off-by: David Leach <david.leach@nxp.com>

soc/nxp/lpc/Kconfig

@@ -0,0 +1,12 @@
+# Copyright 2017,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_LPC
+	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+	select CLOCK_CONTROL
+	select ARM
+
+if SOC_FAMILY_LPC
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_LPC

soc/nxp/lpc/Kconfig.defconfig

@@ -0,0 +1,14 @@
+# Copyright 2017,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_LPC
+
+config SERIAL_INIT_PRIORITY
+	default 55 if SERIAL
+
+config BUILD_WITH_TFM
+	default y if TRUSTED_EXECUTION_NONSECURE
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_LPC

soc/nxp/lpc/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright 2017,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_LPC
+	bool
+
+config SOC_FAMILY
+	default "lpc" if SOC_FAMILY_LPC
+
+rsource "*/Kconfig.soc"

soc/nxp/lpc/lpc11u6x/CMakeLists.txt

@@ -1,7 +1,9 @@
 #
-# Copyright (c) 2017, NXP
+# Copyright 2017, 2024 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/nxp/lpc/lpc11u6x/Kconfig

@@ -1,15 +1,14 @@
 # LPC LPC11U6X MCU line
-
+#
 # Copyright (c) 2020, Seagate
+# Copyright 2024 NXP
+#
 # SPDX-License-Identifier: Apache-2.0
+#
 
 config SOC_SERIES_LPC11U6X
-	bool "LPC LPC11U6X Series MCU"
 	select ARM
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
-	select SOC_FAMILY_LPC
 	select PINCTRL
 	select CLOCK_CONTROL
-	help
-	  Enable support for LPC LPC11U6X MCU series

soc/nxp/lpc/lpc11u6x/Kconfig.defconfig

@@ -1,15 +1,13 @@
-# LPC11U6X series configuration options
-
+# LPC LPC11U6X MCU line
+#
 # Copyright (c) 2020, Seagate
+# Copyright 2024 NXP
+#
 # SPDX-License-Identifier: Apache-2.0
+#
 
 if SOC_SERIES_LPC11U6X
 
-source "soc/soc_legacy/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lp*"
-
-config SOC_SERIES
-	default "lpc11u6x"
-
 config NUM_IRQS
 	# must be >= the highest interrupt number used
 	default 40

soc/nxp/lpc/lpc11u6x/Kconfig.soc

@@ -1,24 +1,34 @@
-# LPC LPC11U6x MCU line
+# NXP LPC11U6x series
 
-# Copyright (c) 2020, Seagate
+# Copyright 2024 NXP
+
+#
 # SPDX-License-Identifier: Apache-2.0
+#
 
-choice
-	prompt "LPC LPC11U6X MCU Selection"
-	depends on SOC_SERIES_LPC11U6X
+config SOC_SERIES_LPC11U6X
+	bool
+	select SOC_FAMILY_LPC
+
+config SOC_SERIES
+	default "lpc11u6x" if SOC_SERIES_LPC11U6X
 
 config SOC_LPC11U68
-	bool "SOC_LPC11U68"
+	bool
+	select SOC_SERIES_LPC11U6X
 
 config SOC_LPC11U67
-	bool "SOC_LPC11U67"
+	bool
+	select SOC_SERIES_LPC11U6X
 
 config SOC_LPC11U66
-	bool "SOC_LPC11U66"
+	bool
+	select SOC_SERIES_LPC11U6X
 
-endchoice
-
-if SOC_SERIES_LPC11U6X
+config SOC
+	default "lpc11u66" if SOC_LPC11U66
+	default "lpc11u67" if SOC_LPC11U67
+	default "lpc11u68" if SOC_LPC11U68
 
 config SOC_PART_NUMBER_LPC11U66JBD48
 	bool
@@ -35,8 +45,7 @@ config SOC_PART_NUMBER_LPC11U68JBD64
 config SOC_PART_NUMBER_LPC11U68JBD100
 	bool
 
-config SOC_PART_NUMBER_LPC11U6X
-	string
+config SOC_PART_NUMBER
 	default "LPC11U66JBD48" if SOC_PART_NUMBER_LPC11U66JBD48
 	default "LPC11U67JBD48" if SOC_PART_NUMBER_LPC11U67JBD48
 	default "LPC11U67JBD64" if SOC_PART_NUMBER_LPC11U67JBD64
@@ -44,9 +53,3 @@ config SOC_PART_NUMBER_LPC11U6X
 	default "LPC11U68JBD48" if SOC_PART_NUMBER_LPC11U68JBD48
 	default "LPC11U68JBD64" if SOC_PART_NUMBER_LPC11U68JBD64
 	default "LPC11U68JBD100" if SOC_PART_NUMBER_LPC11U68JBD100
-
-	help
-	  This string holds the full part number of the SoC. It is a hidden
-	  option that you should not set directly. The part number selection
-	  choice defines the default value for this string.
-endif # SOC_SERIES_LPC11U6X

soc/nxp/lpc/lpc51u68/CMakeLists.txt

@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2021 metraTec GmbH
+# Copyright 2024 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -12,4 +13,6 @@ zephyr_library_include_directories(
   ${ZEPHYR_BASE}/arch/${ARCH}/include
   )
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/nxp/lpc/lpc51u68/Kconfig

@@ -1,19 +1,21 @@
-# LPC LPC51U68 Series
-
+# LPC51U68 series configuration options
+#
 # Copyright (c) 2021 metraTec GmbH
+# Copyright 2024 NXP
+#
 # SPDX-License-Identifier: Apache-2.0
+#
 
 config SOC_SERIES_LPC51U68
-	bool "LPC LPC51U68 Series MCU"
 	select ARM
 	select CPU_CORTEX_M0PLUS
 	select HAS_MCUX
 	select HAS_MCUX_FLEXCOMM
 	select HAS_MCUX_SYSCON
 	select HAS_MCUX_SCTIMER
-	select SOC_FAMILY_LPC
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
 	select PLATFORM_SPECIFIC_INIT
-	help
-	  Enable support for LPC LPC51U68 MCU Series
+
+config SOC_LPC51U68
+	select CLOCK_CONTROL

soc/nxp/lpc/lpc51u68/Kconfig.defconfig

@@ -1,22 +1,17 @@
 # LPC51U68 series configuration options
 
 # Copyright (c) 2021 metraTec GmbH
+# Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_LPC51U68
 
-config SOC_SERIES
-	default "lpc51u68"
-
 config NUM_IRQS
 	# must be >= the highest interrupt number used.
 	default 32
 
-config SOC
-	default "lpc51u68"
-
 config SOC_FLASH_LPC
 	default y
 	depends on FLASH
 
-endif
+endif # SOC_SERIES_LPC51U86

soc/nxp/lpc/lpc51u68/Kconfig.soc

@@ -0,0 +1,29 @@
+# LPC LPC51U68 MCU line
+
+# Copyright (c) 2021 metraTec GmbH
+# Copyright 2024 NXP
+# SPDX-License Identifier: Apache-2.0
+
+config SOC_SERIES_LPC51U68
+	bool
+	select SOC_FAMILY_LPC
+
+config SOC_SERIES
+	default "lpc51u68" if SOC_SERIES_LPC51U68
+
+config SOC_LPC51U68
+	bool
+	select SOC_SERIES_LPC51U68
+
+config SOC
+	default "lpc51u68" if SOC_LPC51U68
+
+config SOC_PART_NUMBER_LPC51U68JBD48
+	bool
+
+config SOC_PART_NUMBER_LPC51U68JBD64
+	bool
+
+config SOC_PART_NUMBER
+	default "LPC51U68JBD48" if SOC_PART_NUMBER_LPC51U68JBD48
+	default "LPC51U68JBD64" if SOC_PART_NUMBER_LPC51U68JBD64

soc/nxp/lpc/lpc54xxx/CMakeLists.txt

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017, NXP
+# Copyright (c) 2017, 2024 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -20,4 +20,6 @@ if(NOT DEFINED CONFIG_LPC54XXX_SRAM2_CLOCK)
 zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1)
 endif()
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/nxp/lpc/lpc54xxx/Kconfig

@@ -0,0 +1,30 @@
+# LPC LPC54XXX MCU line
+
+# Copyright 2017, 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_LPC54XXX
+	select ARM
+	select HAS_MCUX
+	select HAS_MCUX_FLEXCOMM
+	select HAS_MCUX_SYSCON
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select PLATFORM_SPECIFIC_INIT
+
+config SOC_LPC54114_M4
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select PLATFORM_SPECIFIC_INIT
+	select CLOCK_CONTROL
+	select HAS_MCUX_IAP_LEGACY
+
+config SOC_LPC54114_M0
+	select CPU_CORTEX_M0PLUS
+	select CPU_CORTEX_M_HAS_VTOR
+	select CLOCK_CONTROL
+
+config MCUX_CORE_SUFFIX
+	default "_cm4" if SOC_LPC54114_M4
+	default "_cm0plus" if SOC_LPC54114_M0

soc/nxp/lpc/lpc54xxx/Kconfig.defconfig

@@ -0,0 +1,15 @@
+# NXP LPC54114 M0 platform configuration options
+
+# Copyright 2017, 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_LPC54XXX
+
+config GPIO
+	default n if SOC_LPC54114_M0
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	default 40
+
+endif # SOC_SERIES_LPC54XXX

soc/nxp/lpc/lpc54xxx/Kconfig.soc

@@ -1,47 +1,46 @@
 # LPC LPC54XXX MCU line
 
-# Copyright (c) 2017, NXP
+# Copyright (c) 2017, 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-choice
-	prompt "LPC LPC54XXX MCU Selection"
-	depends on SOC_SERIES_LPC54XXX
+config SOC_SERIES_LPC54XXX
+	bool
+	select SOC_FAMILY_LPC
+
+config SOC_SERIES
+	default "lpc54xxx" if SOC_SERIES_LPC54XXX
+
+config SOC_LPC54114
+	bool
+	select SOC_SERIES_LPC54XXX
 
 config SOC_LPC54114_M4
-	bool "SOC_LPC54114_M4"
-	select CPU_CORTEX_M4
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
-	select CLOCK_CONTROL
-	select HAS_MCUX_IAP_LEGACY
+	bool
+	select SOC_LPC54114
 
 config SOC_LPC54114_M0
-	bool "SOC_LPC54114_M0"
-	select CPU_CORTEX_M0PLUS
-	select CPU_CORTEX_M_HAS_VTOR
-	select CLOCK_CONTROL
+	bool
+	select SOC_LPC54114
 
-endchoice
-
-if SOC_SERIES_LPC54XXX
+# The NXP HAL expects the SOC to just be lpc54114 if targeting
+# the M4. When targeting M0 it expects lpc54114_m0.
+#
+# Action to update the NXP HAL to support checking for SOC_LPC54114_M0
+# instead.
+config SOC
+	default "lpc54114" if SOC_LPC54114_M4
+	default "lpc54114" if SOC_LPC54114_M0
 
 config SOC_PART_NUMBER_LPC54114J256BD64
 	bool
 
-config SOC_PART_NUMBER_LPC54XXX
-	string
+config SOC_PART_NUMBER
 	default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64
 
-	help
-	  This string holds the full part number of the SoC. It is a hidden
-	  option that you should not set directly. The part number selection
-	  choice defines the default value for this string.
+if SOC_SERIES_LPC54XXX
 
 config SECOND_CORE_MCUX
 	bool "LPC54114 Cortex-M0 second core"
-	depends on HAS_MCUX
 	help
 	  Driver for second core startup
 

soc/nxp/lpc/lpc55xxx/CMakeLists.txt

@@ -24,4 +24,6 @@ if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS)
 zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1)
 endif()
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/nxp/lpc/lpc55xxx/Kconfig

@@ -0,0 +1,110 @@
+# Copyright 2019,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_LPC55XXX
+	select HAS_MCUX
+	select HAS_MCUX_FLEXCOMM
+	select HAS_MCUX_SYSCON
+	select HAS_MCUX_WWDT
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_DWT
+	select PLATFORM_SPECIFIC_INIT
+
+config SOC_LPC55S06
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
+	select HAS_MCUX_RNG
+
+config SOC_LPC55S16
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
+	select HAS_MCUX_MCAN
+	select HAS_MCUX_RNG
+
+config SOC_LPC55S28
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select HAS_MCUX_IAP
+	select HAS_MCUX_LPADC
+	select HAS_MCUX_LPC_DMA
+	select HAS_MCUX_RNG
+
+config SOC_LPC55S36
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select HAS_MCUX_MCAN
+	select HAS_MCUX_PWM
+
+config SOC_LPC55S69
+	select CPU_CORTEX_M33
+
+config SOC_LPC55S69_CPU0
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select HAS_MCUX_IAP
+	select HAS_MCUX_LPADC
+	select HAS_MCUX_LPC_DMA
+	select HAS_MCUX_USB_LPCIP3511
+	select HAS_MCUX_CTIMER
+	select HAS_MCUX_SCTIMER
+	select HAS_MCUX_RNG
+
+if SOC_SERIES_LPC55XXX
+
+config INIT_PLL0
+	bool "Initialize PLL0"
+
+config INIT_PLL1
+	bool "Initialize PLL1"
+	default "y"
+	depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM)
+	help
+	  In the LPC55XXX Family, this is currently being used to set the
+	  core clock value at it's highest frequency which clocks at 150MHz.
+	  Note that flash programming operations are limited to 100MHz, and
+	  this PLL should not be used as the core clock in those cases.
+
+config SECOND_CORE_MCUX
+	bool "LPC55xxx's second core"
+
+config SECOND_CORE_BOOT_ADDRESS_MCUX
+	depends on SECOND_CORE_MCUX
+	hex "Address the second core will boot at"
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))
+	help
+	  This is the address the second core will boot from.
+
+config LPC55XXX_SRAM_CLOCKS
+	bool "CLock LPC SRAM banks"
+
+config LPC55XXX_USB_RAM
+	bool
+
+if SOC_LPC55S69
+
+config SOC_FLASH_MCUX
+	bool
+
+endif # SOC_LPC55S69
+
+endif # SOC_SERIES_LPC55XXX

soc/nxp/lpc/lpc55xxx/Kconfig.defconfig

@@ -0,0 +1,114 @@
+# Copyright 2019,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_LPC55XXX
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	default 60
+
+# In the LPC55XXX Family, this is currently being used to set the
+# core clock value at it's highest frequency which clocks at 150MHz.
+# Note that flash programming operations are limited to 100MHz, and
+# this PLL should not be used as the core clock in those cases.
+config INIT_PLL1
+	default "y"
+	depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 144000000 if INIT_PLL1
+	default 96000000
+
+# Indicates the second core will be enabled, and the part will run
+# in dual core mode.
+config SECOND_CORE_MCUX
+	depends on HAS_MCUX
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
+
+
+# Move the LMA for the second core image to be in the flash region of primary
+# core, so that JLink flash will load it correctly.
+config BUILD_OUTPUT_ADJUST_LMA
+	depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
+	default "0x10000000"
+
+# SRAM controllers 1,2,3, and 4 are disabled at reset.
+# By default, CMSIS SystemInit will enable the clock to these RAM banks.
+# Disable this Kconfig to leave the ram banks untouched out of reset.
+config LPC55XXX_SRAM_CLOCKS
+	default y
+
+# Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
+# By default, USB RAM is assumed to be present.
+# Disable this Kconfig in case there is no dedicated USB RAM.
+config LPC55XXX_USB_RAM
+	default y
+
+if SOC_LPC55S06
+
+config LPC55XXX_USB_RAM
+	default n
+
+endif # SOC_LPC55S06
+
+if SOC_LPC55S16
+
+config CAN_MCUX_MCAN
+	default y
+	depends on CAN
+
+choice USB_MCUX_CONTROLLER_TYPE
+	default USB_DC_NXP_LPCIP3511
+endchoice
+
+endif # SOC_LPC55S16
+
+if SOC_LPC55S28
+
+choice USB_MCUX_CONTROLLER_TYPE
+	default USB_DC_NXP_LPCIP3511
+endchoice
+
+endif # SOC_LPC55S28
+
+if SOC_LPC55S36
+
+choice USB_MCUX_CONTROLLER_TYPE
+	default USB_DC_NXP_LPCIP3511
+endchoice
+
+config LPC55XXX_USB_RAM
+	default n
+
+endif # SOC_LPC55S36
+
+if SOC_LPC55S69
+
+config SOC_FLASH_MCUX
+	default y
+	depends on FLASH
+	depends on !TRUSTED_EXECUTION_NONSECURE
+
+choice USB_MCUX_CONTROLLER_TYPE
+	default USB_DC_NXP_LPCIP3511
+endchoice
+
+config I2S_MCUX_FLEXCOMM
+	select INIT_PLL0
+
+endif # SOC_LPC55S69
+
+if SOC_LPC55S69_CPU1
+
+
+config GPIO
+	default y
+
+config SERIAL
+	default n
+
+endif # SOC_LPC55S69_CPU1
+
+endif # SOC_SERIES_LPC55XXX

soc/nxp/lpc/lpc55xxx/Kconfig.soc

@@ -0,0 +1,78 @@
+# Copyright 2019, 2023-2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_LPC55XXX
+	bool
+	select SOC_FAMILY_LPC
+
+config SOC_SERIES
+	default "lpc55xxx" if SOC_SERIES_LPC55XXX
+
+config SOC_LPC55S06
+	bool
+	select SOC_SERIES_LPC55XXX
+
+config SOC_LPC55S16
+	bool
+	select SOC_SERIES_LPC55XXX
+
+config SOC_LPC55S28
+	bool
+	select SOC_SERIES_LPC55XXX
+
+config SOC_LPC55S36
+	bool
+	select SOC_SERIES_LPC55XXX
+
+config SOC_LPC55S69
+	bool
+	select SOC_SERIES_LPC55XXX
+
+config SOC_LPC55S69_CPU0
+	bool
+	select SOC_LPC55S69
+
+config SOC_LPC55S69_CPU1
+	bool
+	select SOC_LPC55S69
+
+config MCUX_CORE_SUFFIX
+	default "_cm33_core0" if SOC_LPC55S69_CPU0
+	default "_cm33_core1" if SOC_LPC55S69_CPU1
+
+config SOC
+	default "lpc55s69" if SOC_LPC55S69_CPU0 || SOC_LPC55S69_CPU1
+	default "lpc55s06" if SOC_LPC55S06
+	default "lpc55s16" if SOC_LPC55S16
+	default "lpc55s28" if SOC_LPC55S28
+	default "lpc55s36" if SOC_LPC55S36
+
+config SOC_PART_NUMBER_LPC55S06JBD64
+	bool
+
+config SOC_PART_NUMBER_LPC55S16JBD64
+	bool
+
+config SOC_PART_NUMBER_LPC55S16JBD100
+	bool
+
+config SOC_PART_NUMBER_LPC55S28JBD100
+	bool
+
+config SOC_PART_NUMBER_LPC55S36JBD100
+	bool
+
+config SOC_PART_NUMBER_LPC55S69JBD100
+	bool
+
+config SOC_PART_NUMBER_LPC55S69JET98
+	bool
+
+config SOC_PART_NUMBER
+	default "LPC55S06JBD64"  if SOC_PART_NUMBER_LPC55S06JBD64
+	default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64
+	default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100
+	default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100
+	default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100
+	default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100
+	default "LPC55S69JET98"  if SOC_PART_NUMBER_LPC55S69JET98

soc/nxp/lpc/soc.yml

@@ -0,0 +1,27 @@
+family:
+- name: lpc
+  series:
+  - name: lpc11u6x
+    socs:
+    - name: lpc11u66
+    - name: lpc11u67
+    - name: lpc11u68
+  - name: lpc51u68
+    socs:
+    - name: lpc51u68
+  - name: lpc54xxx
+    socs:
+    - name: lpc54114
+      cpuclusters:
+      - name: m4
+      - name: m0
+  - name: lpc55xxx
+    socs:
+    - name: lpc55s06
+    - name: lpc55s16
+    - name: lpc55s28
+    - name: lpc55s36
+    - name: lpc55s69
+      cpuclusters:
+      - name: cpu0
+      - name: cpu1

soc/soc_legacy/arm/nxp_lpc/Kconfig

@@ -1,22 +0,0 @@
-# Copyright (c) 2017, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_LPC
-	bool
-	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
-
-if SOC_FAMILY_LPC
-
-config SOC_FAMILY
-	string
-	default "nxp_lpc"
-
-source "soc/soc_legacy/arm/nxp_lpc/*/Kconfig.soc"
-
-config SOC_PART_NUMBER
-	default SOC_PART_NUMBER_LPC54XXX if SOC_SERIES_LPC54XXX
-	default SOC_PART_NUMBER_LPC55XXX if SOC_SERIES_LPC55XXX
-	default SOC_PART_NUMBER_LPC11U6X if SOC_SERIES_LPC11U6X
-	default SOC_PART_NUMBER_LPC51U68 if SOC_SERIES_LPC51U68
-
-endif # SOC_FAMILY_LPC

soc/soc_legacy/arm/nxp_lpc/Kconfig.defconfig

@@ -1,8 +0,0 @@
-# Copyright (c) 2017, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/arm/nxp_lpc/*/Kconfig.defconfig.series"
-
-config SERIAL_INIT_PRIORITY
-	default 55
-	depends on SERIAL

soc/soc_legacy/arm/nxp_lpc/Kconfig.soc

@@ -1,4 +0,0 @@
-# Copyright (c) 2017, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/arm/nxp_lpc/*/Kconfig.series"

soc/soc_legacy/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u66

@@ -1,11 +0,0 @@
-# NXP LPC11U66 platform configuration options
-
-# Copyright (c) 2020, Seagate
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC11U66
-
-config SOC
-	default "lpc11u66"
-
-endif # SOC_LPC11U66

soc/soc_legacy/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u67

@@ -1,11 +0,0 @@
-# NXP LPC11U67 platform configuration options
-
-# Copyright (c) 2020, Seagate
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC11U67
-
-config SOC
-	default "lpc11u67"
-
-endif # SOC_LPC11U67

soc/soc_legacy/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u68

@@ -1,11 +0,0 @@
-# NXP LPC11U68 platform configuration options
-
-# Copyright (c) 2020, Seagate
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC11U68
-
-config SOC
-	default "lpc11u68"
-
-endif # SOC_LPC11U68

soc/soc_legacy/arm/nxp_lpc/lpc51u68/Kconfig.soc

@@ -1,27 +0,0 @@
-# LPC LPC51U68 MCU line
-
-# Copyright (c) 2021 metraTec GmbH
-# SPDX-License Identifier: Apache-2.0
-
-config SOC_LPC51U68
-	bool "SOC_LPC51U68"
-	depends on SOC_SERIES_LPC51U68
-	select CLOCK_CONTROL
-
-if SOC_SERIES_LPC51U68
-
-config SOC_PART_NUMBER_LPC51U68JBD48
-	bool
-config SOC_PART_NUMBER_LPC51U68JBD64
-	bool
-
-config SOC_PART_NUMBER_LPC51U68
-	string
-	default "LPC51U68JBD48" if SOC_PART_NUMBER_LPC51U68JBD48
-	default "LPC51U68JBD64" if SOC_PART_NUMBER_LPC51U68JBD64
-	help
-	  This string holds the full part number of the SoC. It is a hidden
-	  option that you should not set directly. The part number selection
-	  choice defines the default value for this string.
-
-endif # SOC_SERIES_LPC51U68

soc/soc_legacy/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0

@@ -1,14 +0,0 @@
-# NXP LPC54114 M0 platform configuration options
-
-# Copyright (c) 2017, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC54114_M0
-
-config SOC
-	default "lpc54114_m0"
-
-config GPIO
-	default n
-
-endif # SOC_LPC54114_M0

soc/soc_legacy/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m4

@@ -1,11 +0,0 @@
-# NXP LPC54114 platform configuration options
-
-# Copyright (c) 2017, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC54114_M4
-
-config SOC
-	default "lpc54114"
-
-endif # SOC_LPC54114_M4

soc/soc_legacy/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.series

@@ -1,17 +0,0 @@
-# LPC54XXX series configuration options
-
-# Copyright (c) 2017, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_LPC54XXX
-
-config SOC_SERIES
-	default "lpc54xxx"
-
-config NUM_IRQS
-	# must be >= the highest interrupt number used
-	default 40
-
-source "soc/soc_legacy/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lp*"
-
-endif # SOC_SERIES_LPC54XXX

soc/soc_legacy/arm/nxp_lpc/lpc54xxx/Kconfig.series

@@ -1,16 +0,0 @@
-# LPC LPC54XXX MCU line
-
-# Copyright (c) 2017, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_LPC54XXX
-	bool "LPC LPC54xxx Series MCU"
-	select ARM
-	select HAS_MCUX
-	select HAS_MCUX_FLEXCOMM
-	select HAS_MCUX_SYSCON
-	select SOC_FAMILY_LPC
-	select CPU_CORTEX_M_HAS_SYSTICK
-	select PLATFORM_SPECIFIC_INIT
-	help
-	  Enable support for LPC LPC54XXX MCU series

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S06

@@ -1,14 +0,0 @@
-# NXP LPC55S06 platform configuration options
-
-# Copyright (c) 2022 metraTec
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC55S06
-
-config SOC
-	default "lpc55S06"
-
-config LPC55XXX_USB_RAM
-	default n
-
-endif # SOC_LPC55S06

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16

@@ -1,19 +0,0 @@
-# NXP LPC55S16 platform configuration options
-
-# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC55S16
-
-config SOC
-	default "lpc55S16"
-
-config CAN_MCUX_MCAN
-	default y
-	depends on CAN
-
-choice USB_MCUX_CONTROLLER_TYPE
-	default USB_DC_NXP_LPCIP3511
-endchoice
-
-endif # SOC_LPC55S16

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S28

@@ -1,15 +0,0 @@
-# NXP LPC55S28 platform configuration options
-
-# Copyright (c) 2020 Lemonbeat GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC55S28
-
-config SOC
-	default "lpc55S28"
-
-choice USB_MCUX_CONTROLLER_TYPE
-	default USB_DC_NXP_LPCIP3511
-endchoice
-
-endif # SOC_LPC55S28

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S36

@@ -1,18 +0,0 @@
-# NXP LPC55S36 platform configuration options
-
-# Copyright 2022 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC55S36
-
-config SOC
-	default "lpc55S36"
-
-choice USB_MCUX_CONTROLLER_TYPE
-	default USB_DC_NXP_LPCIP3511
-endchoice
-
-config LPC55XXX_USB_RAM
-	default n
-
-endif # SOC_LPC55S36

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0

@@ -1,23 +0,0 @@
-# NXP LPC55XXX CPU0 platform configuration options
-
-# Copyright (c) 2019, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC55S69_CPU0
-
-config SOC
-	default "lpc55S69_cpu0"
-
-config SOC_FLASH_MCUX
-	default y
-	depends on FLASH
-	depends on !TRUSTED_EXECUTION_NONSECURE
-
-choice USB_MCUX_CONTROLLER_TYPE
-	default USB_DC_NXP_LPCIP3511
-endchoice
-
-config I2S_MCUX_FLEXCOMM
-	select INIT_PLL0
-
-endif # SOC_LPC55S69_CPU0

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1

@@ -1,17 +0,0 @@
-# NXP LPC55S69 CPU1 platform configuration options
-
-# Copyright (c) 2019, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_LPC55S69_CPU1
-
-config SOC
-	default "lpc55S69_cpu1"
-
-config GPIO
-	default y
-
-config SERIAL
-	default n
-
-endif # SOC_LPC55S69_CPU1

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series

@@ -1,17 +0,0 @@
-# LPC55XXX series configuration options
-
-# Copyright (c) 2019, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_LPC55XXX
-
-config SOC_SERIES
-	default "lpc55xxx"
-
-config NUM_IRQS
-	# must be >= the highest interrupt number used
-	default 60
-
-source "soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lp*"
-
-endif # SOC_SERIES_LPC55XXX

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.series

@@ -1,18 +0,0 @@
-# LPC LPC55XXX Series
-
-# Copyright (c) 2019, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_LPC55XXX
-	bool "LPC5500 Series Family MCU"
-	select ARM
-	select HAS_MCUX
-	select HAS_MCUX_FLEXCOMM
-	select HAS_MCUX_SYSCON
-	select HAS_MCUX_WWDT
-	select SOC_FAMILY_LPC
-	select CPU_CORTEX_M_HAS_SYSTICK
-	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
-	help
-	  Enable support for LPC5500 Series MCU series

soc/soc_legacy/arm/nxp_lpc/lpc55xxx/Kconfig.soc

@@ -1,177 +0,0 @@
-# LPC LPC55XXX Series
-
-# Copyright 2019, 2023 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "LPC5500 Series MCU Selection"
-	depends on SOC_SERIES_LPC55XXX
-
-config SOC_LPC55S06
-	bool "SOC_LPC55S06 M33"
-	select CPU_CORTEX_M33
-	select CPU_HAS_ARM_SAU
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU
-	select ARMV8_M_DSP
-	select ARM_TRUSTZONE_M
-	select CLOCK_CONTROL
-	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
-	select HAS_MCUX_RNG
-
-config SOC_LPC55S16
-	bool "SOC_LPC55S16 M33"
-	select CPU_CORTEX_M33
-	select CPU_HAS_ARM_SAU
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU
-	select ARMV8_M_DSP
-	select ARM_TRUSTZONE_M
-	select CLOCK_CONTROL
-	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
-	select HAS_MCUX_MCAN
-	select HAS_MCUX_RNG
-
-config SOC_LPC55S28
-	bool "SOC_LPC55S28 M33"
-	select CPU_CORTEX_M33
-	select CPU_HAS_ARM_SAU
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU
-	select ARMV8_M_DSP
-	select CLOCK_CONTROL
-	select HAS_MCUX_IAP
-	select HAS_MCUX_LPADC
-	select HAS_MCUX_LPC_DMA
-	select HAS_MCUX_RNG
-
-config SOC_LPC55S36
-	bool "SOC_LPC55S36 M33"
-	select CPU_CORTEX_M33
-	select CPU_HAS_ARM_SAU
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU
-	select ARMV8_M_DSP
-	select ARM_TRUSTZONE_M
-	select CLOCK_CONTROL
-	select HAS_MCUX_MCAN
-	select HAS_MCUX_PWM
-
-config SOC_LPC55S69_CPU0
-	bool "SOC_LPC55S69 M33 [CPU 0]"
-	select CPU_CORTEX_M33
-	select CPU_HAS_ARM_SAU
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU
-	select ARMV8_M_DSP
-	select ARM_TRUSTZONE_M
-	select CLOCK_CONTROL
-	select HAS_MCUX_IAP
-	select HAS_MCUX_LPADC
-	select HAS_MCUX_LPC_DMA
-	select HAS_MCUX_USB_LPCIP3511
-	select HAS_MCUX_CTIMER
-	select HAS_MCUX_SCTIMER
-	select HAS_MCUX_RNG
-
-config SOC_LPC55S69_CPU1
-	bool "SOC_LPC55S69 M33 [CPU 1]"
-	select CPU_CORTEX_M33
-
-endchoice
-
-if SOC_SERIES_LPC55XXX
-
-config SOC_PART_NUMBER_LPC55S06JBD64
-	bool
-
-config SOC_PART_NUMBER_LPC55S16JBD64
-	bool
-
-config SOC_PART_NUMBER_LPC55S16JBD100
-	bool
-
-config SOC_PART_NUMBER_LPC55S28JBD100
-	bool
-
-config SOC_PART_NUMBER_LPC55S36JBD100
-	bool
-
-config SOC_PART_NUMBER_LPC55S69JBD100
-	bool
-
-config SOC_PART_NUMBER_LPC55S69JET98
-	bool
-
-config SOC_PART_NUMBER_LPC55XXX
-	string
-	default "LPC55S06JBD64"  if SOC_PART_NUMBER_LPC55S06JBD64
-	default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64
-	default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100
-	default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100
-	default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100
-	default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100
-	default "LPC55S69JET98"  if SOC_PART_NUMBER_LPC55S69JET98
-
-	help
-	  This string holds the full part number of the SoC. It is a hidden
-	  option that you should not set directly. The part number selection
-	  choice defines the default value for this string.
-
-config INIT_PLL0
-	bool "Initialize PLL0"
-
-config INIT_PLL1
-	bool "Initialize PLL1"
-	default "y"
-	depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM)
-	help
-	  In the LPC55XXX Family, this is currently being used to set the
-	  core clock value at it's highest frequency which clocks at 150MHz.
-	  Note that flash programming operations are limited to 100MHz, and
-	  this PLL should not be used as the core clock in those cases.
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 144000000 if INIT_PLL1
-	default 96000000
-
-config SECOND_CORE_MCUX
-	bool "LPC55xxx's second core"
-	depends on HAS_MCUX
-	help
-	  Indicates the second core will be enabled, and the part will run
-	  in dual core mode.
-
-# Workaround for not being able to have commas in macro arguments
-DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
-
-config SECOND_CORE_BOOT_ADDRESS_MCUX
-	depends on SECOND_CORE_MCUX
-	hex "Address the second core will boot at"
-	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))
-	help
-	  This is the address the second core will boot from.
-
-# Move the LMA for the second core image to be in the flash region of primary
-# core, so that JLink flash will load it correctly.
-config BUILD_OUTPUT_ADJUST_LMA
-	depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
-	default "0x10000000"
-
-config LPC55XXX_SRAM_CLOCKS
-	bool "CLock LPC SRAM banks"
-	default y
-	help
-	  SRAM controllers 1,2,3, and 4 are disabled at reset.
-	  By default, CMSIS SystemInit will enable the clock to these RAM banks.
-	  Disable this Kconfig to leave the ram banks untouched out of reset.
-
-config LPC55XXX_USB_RAM
-	bool
-	default y
-	help
-	  Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
-	  By default, USB RAM is assumed to be present.
-	  Disable this Kconfig in case there is no dedicated USB RAM.
-
-endif # SOC_SERIES_LPC55XXX