From 261dfbc765c7f88d12106230022cb0d4967788f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C5=81ukasz=20K=C4=99dziora?= <lkedziora@antmicro.com>
Date: Wed, 29 Oct 2025 11:00:28 +0100
Subject: [PATCH] drivers: spi_dw: Add clock control
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This adds optional clock control support to the spi_dw driver. The
support currently assumes that the clock control binding uses clkid for
the clock cell name.

Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
---
 drivers/spi/spi_dw.c | 20 ++++++++++++++++++++
 drivers/spi/spi_dw.h |  8 ++++++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c
index 9f00905a3f0..587342931ae 100644
--- a/drivers/spi/spi_dw.c
+++ b/drivers/spi/spi_dw.c
@@ -558,6 +558,16 @@ int spi_dw_init(const struct device *dev)
 	pinctrl_apply_state(info->pcfg, PINCTRL_STATE_DEFAULT);
 #endif
 
+#if defined(CONFIG_CLOCK_CONTROL)
+	if (info->clk_dev) {
+		err = clock_control_on(info->clk_dev, info->clk_id);
+		if (err < 0) {
+			LOG_ERR("Failed to enable the clock");
+			return err;
+		}
+	}
+#endif
+
 	DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
 
 	info->config_func();
@@ -649,6 +659,15 @@ COND_CODE_1(IS_EQ(DT_NUM_IRQS(DT_DRV_INST(inst)), 1),              \
 		(SPI_CFG_IRQS_MULTIPLE_ERR_LINES(inst)))))	   \
 }
 
+#if defined(CONFIG_CLOCK_CONTROL)
+#define CLOCK_DW_CONFIG(n)                                                             \
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(0, clocks),                                   \
+		   (.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                  \
+		    .clk_id = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, clkid),))
+#else
+#define CLOCK_DW_CONFIG(n)
+#endif
+
 #define SPI_DW_INIT(inst)                                                                   \
 	IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(inst);))                         \
 	SPI_DW_IRQ_HANDLER(inst);                                                           \
@@ -679,6 +698,7 @@ COND_CODE_1(IS_EQ(DT_NUM_IRQS(DT_DRV_INST(inst)), 1),              \
 			.set_bit_func = reg_set_bit,                                        \
 			.clear_bit_func = reg_clear_bit,                                    \
 			.test_bit_func = reg_test_bit,))                                    \
+		CLOCK_DW_CONFIG(inst)                                                      \
 	};                                                                                  \
 	SPI_DEVICE_DT_INST_DEFINE(inst,                                                     \
 		spi_dw_init,                                                                \
diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h
index c91ddbf7996..0868cd50dde 100644
--- a/drivers/spi/spi_dw.h
+++ b/drivers/spi/spi_dw.h
@@ -14,6 +14,10 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/spi.h>
 
+#if defined(CONFIG_CLOCK_CONTROL)
+#include <zephyr/drivers/clock_control.h>
+#endif
+
 #include "spi_context.h"
 
 #ifdef __cplusplus
@@ -46,6 +50,10 @@ struct spi_dw_config {
 	uint8_t max_xfer_size;
 #ifdef CONFIG_PINCTRL
 	const struct pinctrl_dev_config *pcfg;
+#endif
+#if defined(CONFIG_CLOCK_CONTROL)
+	const struct device *clk_dev;
+	const clock_control_subsys_t clk_id;
 #endif
 	spi_dw_read_t read_func;
 	spi_dw_write_t write_func;