boards: riscv: rv32m1_vega: Convert to v2

Converts the board to hwmv2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

boards/boards_legacy/riscv/rv32m1_vega/Kconfig.board

@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_RV32M1_VEGA
-	bool "RV32M1 RISC-V cores"
-	depends on SOC_OPENISA_RV32M1_RISCV32

boards/boards_legacy/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig

@@ -1,10 +0,0 @@
-CONFIG_SOC_OPENISA_RV32M1_RISCV32=y
-CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY=y
-CONFIG_BOARD_RV32M1_VEGA=y
-CONFIG_GPIO=y
-CONFIG_PINCTRL=y
-CONFIG_SERIAL=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-CONFIG_MULTI_LEVEL_INTERRUPTS=y

boards/openisa/rv32m1_vega/Kconfig.defconfig

@@ -2,10 +2,6 @@
 
 if BOARD_RV32M1_VEGA
 
-config BOARD
-	default "rv32m1_vega_ri5cy" if SOC_OPENISA_RV32M1_RI5CY
-	default "rv32m1_vega_zero_riscy" if SOC_OPENISA_RV32M1_ZERO_RISCY
-
 if BT
 
 config BT_CTLR

boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega

@@ -0,0 +1,6 @@
+# Copyright 2018 Foundries.io Ltd
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RV32M1_VEGA
+	select SOC_OPENISA_RV32M1_RI5CY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_RI5CY
+	select SOC_OPENISA_RV32M1_ZERO_RISCY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_ZERO_RISCY

boards/openisa/rv32m1_vega/board.cmake

@@ -3,9 +3,9 @@
 set(OPENOCD_USE_LOAD_IMAGE NO)
 
 if(CONFIG_SOC_OPENISA_RV32M1_RI5CY)
-board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg")
+  board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg")
 elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY)
-board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg")
+  board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg")
 endif()
 
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/openisa/rv32m1_vega/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: rv32m1_vega
+  vendor: OpenISA
+  socs:
+  - name: openisa_rv32m1

boards/openisa/rv32m1_vega/doc/index.rst

@@ -27,8 +27,8 @@ flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a
 coprocessor for applications running on RI5CY. The two cores can
 communicate via shared memory and messaging peripherals.
 
-Currently, Zephyr supports RI5CY with the ``rv32m1_vega_ri5cy`` board
-configuration name, and ZERO_RISCY with the ``rv32m1_vega_zero_riscy`` board
+Currently, Zephyr supports RI5CY with the ``rv32m1_vega/openisa_rv32m1/ri5cy`` board
+configuration name, and ZERO_RISCY with the ``rv32m1_vega/openisa_rv32m1/zero_riscy`` board
 configuration name.
 
 Hardware
@@ -68,7 +68,7 @@ Additional features:
 Supported Features
 ==================
 
-Zephyr's RI5CY configuration, ``rv32m1_vega_ri5cy``, currently supports
+Zephyr's RI5CY configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``, currently supports
 the following hardware features:
 
 +-----------+------------+-------------------------------------+
@@ -96,7 +96,7 @@ the following hardware features:
 |           |            | fxos8700 trigger;                   |
 +-----------+------------+-------------------------------------+
 
-Zephyr's ZERO-RISCY configuration, ``rv32m1_vega_zero_riscy``, currently
+Zephyr's ZERO-RISCY configuration, ``rv32m1_vega/openisa_rv32m1/zero_riscy``, currently
 supports the following hardware features:
 
 +-----------+------------+-------------------------------------+
@@ -125,7 +125,7 @@ supports the following hardware features:
 BLE Software Link Layer experimental support
 ==================================================
 This is an experimental feature supported on the Zephyr's RI5CY
-configuration, ``rv32m1_vega_ri5cy``. It  uses the Software Link Layer
+configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``. It  uses the Software Link Layer
 framework by Nordic Semi to enable the on-SoC radio and transceiver for
 implementing a software defined BLE controller. By using both the controller
 and the host stack available in Zephyr, the following BLE samples can be used
@@ -313,8 +313,8 @@ Additional Pins
 For an up-to-date description of additional pins (such as buttons,
 LEDs, etc.) supported by Zephyr, see the board DTS files in the Zephyr
 source code, i.e.
-:zephyr_file:`boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts` for RI5CY and
-:zephyr_file:`boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts` for
+:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts` for RI5CY and
+:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts` for
 ZERO-RISCY.
 
 See the schematic in the documentation available from the `OpenISA
@@ -494,13 +494,13 @@ first make sure you're booting the right core.
 
 1. In one terminal, use OpenOCD to connect to the board::
 
-     ~/rv32m1-openocd -f boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
+     ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
 
    The output should look like this:
 
    .. code-block:: console
 
-      $ ~/rv32m1-openocd -f boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
+      $ ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
       Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29)
       [...]
       Info : Listening on port 3333 for gdb connections
@@ -537,7 +537,7 @@ first make sure you're booting the right core.
 
 In one cmd.exe prompt in the Zephyr directory::
 
- C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\riscv32\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg
+ C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\openisa\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg
 
 In a telnet program of your choice:
 
@@ -596,7 +596,7 @@ Linux and macOS (run this in a terminal from the Zephyr directory)::
    :zephyr-app: samples/hello_world
    :tool: cmake
    :cd-into:
-   :board: rv32m1_vega_ri5cy
+   :board: rv32m1_vega/openisa_rv32m1/ri5cy
    :gen-args: -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=/dev/null
    :goals: build
 
@@ -609,7 +609,7 @@ Windows (run this in a ``cmd`` prompt, from the Zephyr directory)::
 
   # Use CMake to generate a Ninja-based build system:
   type NUL > empty.ld
-  cmake -GNinja -DBOARD=rv32m1_vega_ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.ld ..
+  cmake -GNinja -DBOARD=rv32m1_vega/openisa_rv32m1/ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.ld ..
 
   # Build the sample
   ninja

boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi

@@ -3,7 +3,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "rv32m1_vega-pinctrl.dtsi"
+#include "rv32m1_vega_openisa_rv32m1-pinctrl.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {

boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig

@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_OPENISA_RV32M1_RISCV32=y
-CONFIG_SOC_OPENISA_RV32M1_RI5CY=y
-CONFIG_BOARD_RV32M1_VEGA=y
 CONFIG_GPIO=y
 CONFIG_PINCTRL=y
 CONFIG_SERIAL=y

boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts

@@ -6,7 +6,7 @@
 /dts-v1/;
 
 #include "openisa/rv32m1_ri5cy.dtsi"
-#include "rv32m1_vega.dtsi"
+#include "rv32m1_vega_openisa_rv32m1.dtsi"
 
 / {
 	model = "OpenISA RV32M1 Vega RI5CY";

boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml

@@ -1,4 +1,4 @@
-identifier: rv32m1_vega_ri5cy
+identifier: rv32m1_vega/openisa_rv32m1/ri5cy
 name: RV32M1-VEGA (RI5CY)
 type: mcu
 arch: riscv

boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts

@@ -6,7 +6,7 @@
 /dts-v1/;
 
 #include "openisa/rv32m1_zero_riscy.dtsi"
-#include "rv32m1_vega.dtsi"
+#include "rv32m1_vega_openisa_rv32m1.dtsi"
 
 / {
 	model = "OpenISA RV32M1 Vega Zero RISCY";

boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml

@@ -1,4 +1,4 @@
-identifier: rv32m1_vega_zero_riscy
+identifier: rv32m1_vega/openisa_rv32m1/zero_riscy
 name: RV32M1-VEGA (ZERO-RISCY)
 type: mcu
 arch: riscv