soc: qemu_cortex_a53: Port to HWMv2

Ports the qemu_cortex_a53 SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/v2/arm/CMakeLists.txt

@@ -1,4 +1,8 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-add_subdirectory(${SOC_SERIES})
+if(DEFINED SOC_SERIES)
+  add_subdirectory(${SOC_SERIES})
+else()
+  add_subdirectory(${SOC_NAME})
+endif()

soc/v2/arm/qemu_cortex_a53/CMakeLists.txt

@@ -3,4 +3,6 @@
 
 zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/v2/arm/qemu_cortex_a53/Kconfig

@@ -2,6 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_QEMU_CORTEX_A53
-	bool "QEMU virt platform (cortex-a53)"
 	select ARM64
 	select CPU_CORTEX_A53
+	select QEMU_TARGET

soc/v2/arm/qemu_cortex_a53/Kconfig.defconfig

@@ -3,9 +3,6 @@
 
 if SOC_QEMU_CORTEX_A53
 
-config SOC
-	default "qemu_cortex_a53"
-
 config NUM_IRQS
 	# must be >= the highest interrupt number used
 	# - include the UART interrupts

soc/v2/arm/qemu_cortex_a53/Kconfig.soc

@@ -0,0 +1,9 @@
+# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_CORTEX_A53
+	bool
+	select SOC_FAMILY_ARM64
+
+config SOC
+	default "qemu_cortex_a53" if SOC_QEMU_CORTEX_A53

soc/v2/arm/soc.yml

@@ -7,3 +7,5 @@ family:
   - name: fvp_aemv8r
     socs:
     - name: fvp_aemv8r_aarch64
+  socs:
+  - name: qemu_cortex_a53