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soc: nxp: port imx8mq SOC to HWMv2

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Port IMX8M Quad SOC to HWMv2. Only the M4 core is enabled.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse
2024-03-01 00:57:15 +00:00
committed by Jamie
parent 8ea02f4e63
commit 3ec2299c62
21 changed files with 48 additions and 204 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clock_control/clock_control_mcux_syscon.c
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@@ -27,7 +27,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
if ((uint32_t)sub_system == MCUX_MRT_CLK) {
#if defined(CONFIG_SOC_FAMILY_LPC)
CLOCK_EnableClock(kCLOCK_Mrt);
#elif defined(CONFIG_SOC_FAMILY_IMX)
#elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT)
CLOCK_EnableClock(kCLOCK_Mrt0);
#endif
}

2
drivers/gpio/gpio_mcux_igpio.c
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@@ -152,7 +152,7 @@ static int mcux_igpio_configure(const struct device *dev,
}
#elif defined(CONFIG_SOC_SERIES_IMX8MQ_M4)
#elif defined(CONFIG_SOC_MIMX8MQ6_M4)
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);

2
modules/Kconfig.imx
View File

@@ -6,7 +6,7 @@
config HAS_IMX_HAL
bool
select HAS_CMSIS_CORE
depends on SOC_FAMILY_NXP_IMX || SOC_FAMILY_IMX
depends on SOC_FAMILY_NXP_IMX
if HAS_IMX_HAL

2
modules/Kconfig.mcux
View File

@@ -6,7 +6,7 @@
config HAS_MCUX
bool
depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \
SOC_FAMILY_NXP_S32 || SOC_FAMILY_IMX || SOC_FAMILY_NXP_IMXRT
SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT
if HAS_MCUX
config MCUX_CORE_SUFFIX

4
soc/nxp/imx/imx8m/CMakeLists.txt
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@@ -43,6 +43,10 @@ if(CONFIG_SOC_MIMX8MM6_M4)
add_subdirectory(m4_mini)
endif()
if(CONFIG_SOC_MIMX8MQ6_M4)
add_subdirectory(m4_quad)
endif()
if(CONFIG_SOC_MIMX8MP_M7)
add_subdirectory(m7)
endif()

10
soc/nxp/imx/imx8m/Kconfig
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@@ -65,6 +65,16 @@ config SOC_MIMX8MP_M7
select HAS_MCUX_IGPIO
select HAS_MCUX_IOMUXC
config SOC_MIMX8MQ6_M4
select ARM
select CPU_CORTEX_M4
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_MCUX
select HAS_MCUX_CCM
select HAS_MCUX_RDC
select HAS_MCUX_IOMUXC
config MCUX_CORE_SUFFIX
default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53
default "_dsp" if SOC_MIMX8MP_ADSP

16
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 → soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4
View File

@@ -1,13 +1,10 @@
# MIMX8MQ6 SoC defconfig
# MIMX8MQ6 M4 SoC defconfig
# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMX8MQ6
config SOC
string
default "mimx8mq6"
if SOC_MIMX8MQ6_M4
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
@@ -17,4 +14,9 @@ config PINCTRL_IMX
default y if HAS_MCUX_IOMUXC
depends on PINCTRL
endif # SOC_MIMX8MQ6
config NUM_IRQS
int
# must be >= the highest interrupt number used
default 127
endif # SOC_MIMX8MQ6_M4

15
soc/nxp/imx/imx8m/Kconfig.soc
View File

@@ -50,6 +50,16 @@ config SOC_MIMX8MP_M7
help
Enable support for NXP i.MX 8MPLUS M7 MCU
config SOC_MIMX8MQ6
bool
select SOC_SERIES_IMX8M
config SOC_MIMX8MQ6_M4
bool
select SOC_MIMX8MQ6
help
Enable support for NXP i.MX 8M Quad M4 MCU
config SOC_TOOLCHAIN_NAME
string
default "nxp_imx8m_adsp" if SOC_MIMX8MP_ADSP
@@ -68,6 +78,7 @@ config SOC
default "mimx8mm6" if SOC_MIMX8MM6
default "mimx8mn6" if SOC_MIMX8MN6
default "mimx8ml8" if SOC_MIMX8MP
default "mimx8mq6" if SOC_MIMX8MQ6
config SOC_PART_NUMBER_MIMX8ML8DVNLZ
bool
@@ -90,6 +101,9 @@ config SOC_PART_NUMBER_MIMX8MN6CVTIZ
config SOC_PART_NUMBER_MIMX8MN6CUCIZ
bool
config SOC_PART_NUMBER_MIMX8MQ6DVAJZ
bool
config SOC_PART_NUMBER
default "MIMX8ML8DVNLZ" if SOC_PART_NUMBER_MIMX8ML8DVNLZ
default "MIMX8MM6DVTLZ" if SOC_PART_NUMBER_MIMX8MM6DVTLZ
@@ -98,3 +112,4 @@ config SOC_PART_NUMBER
default "MIMX8MN6DUCJZ" if SOC_PART_NUMBER_MIMX8MN6DUCJZ
default "MIMX8MN6CVTIZ" if SOC_PART_NUMBER_MIMX8MN6CVTIZ
default "MIMX8MN6CUCIZ" if SOC_PART_NUMBER_MIMX8MN6CUCIZ
default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ

2
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt → soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt
View File

@@ -1,5 +1,6 @@
#
# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
@@ -7,5 +8,6 @@
zephyr_sources(
soc.c
)
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

0
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/pinctrl_soc.h → soc/nxp/imx/imx8m/m4_quad/pinctrl_soc.h
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0
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/soc.c → soc/nxp/imx/imx8m/m4_quad/soc.c
View File

0
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/soc.h → soc/nxp/imx/imx8m/m4_quad/soc.h
View File

4
soc/nxp/imx/soc.yml
View File

@@ -38,6 +38,10 @@ family:
cpuclusters:
- name: a53
- name: m7
- name: mimx8mq6
cpuclusters:
- name: a53
- name: m4
- name: imx9
socs:
- name: mimx9352

7
soc/soc_legacy/arm/nxp_imx/CMakeLists.txt
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@@ -1,7 +0,0 @@
#
# Copyright (c) 2017, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
add_subdirectory(${SOC_SERIES})

45
soc/soc_legacy/arm/nxp_imx/Kconfig
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@@ -1,45 +0,0 @@
# Copyright (c) 2017-2021, NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_IMX
bool
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
if SOC_FAMILY_IMX
config SOC_FAMILY
string
default "nxp_imx"
# Used for default value in FLASH_MCUX_FLEXSPI_XIP
DT_CHOSEN_Z_FLASH := zephyr,flash
DT_COMPAT_FLEXSPI := nxp,imx-flexspi
# Macros to shorten Kconfig definitions
DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
source "soc/soc_legacy/arm/nxp_imx/*/Kconfig.soc"
config SOC_PART_NUMBER
default SOC_PART_NUMBER_IMX_RT5XX if SOC_SERIES_IMX_RT5XX
default SOC_PART_NUMBER_IMX_RT6XX if SOC_SERIES_IMX_RT6XX
default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT
default SOC_PART_NUMBER_IMX_6X_M4 if SOC_SERIES_IMX_6X_M4
default SOC_PART_NUMBER_IMX7_M4 if SOC_SERIES_IMX7_M4
default SOC_PART_NUMBER_IMX8MM_M4 if SOC_SERIES_IMX8MM_M4
default SOC_PART_NUMBER_IMX8ML_M7 if SOC_SERIES_IMX8ML_M7
default SOC_PART_NUMBER_IMX8MQ_M4 if SOC_SERIES_IMX8MQ_M4
config FLASH_MCUX_FLEXSPI_XIP
bool "MCUX FlexSPI flash access with xip"
default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
depends on (CODE_FLEXSPI || CODE_FLEXSPI2 || SOC_SERIES_IMX_RT6XX || SOC_SERIES_IMX_RT5XX)
select XIP
help
Allows for the soc to safely initialize the clocks for the
FlexSpi when planning to execute code in FlexSpi Memory.
endif # SOC_FAMILY_IMX

8
soc/soc_legacy/arm/nxp_imx/Kconfig.defconfig
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@@ -1,8 +0,0 @@
# Copyright (c) 2017, NXP
# SPDX-License-Identifier: Apache-2.0
config SERIAL_INIT_PRIORITY
default 55
depends on SERIAL
source "soc/soc_legacy/arm/nxp_imx/*/Kconfig.defconfig.series"

4
soc/soc_legacy/arm/nxp_imx/Kconfig.soc
View File

@@ -1,4 +0,0 @@
# Copyright (c) 2017, NXP
# SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/arm/nxp_imx/*/Kconfig.series"

18
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.series
View File

@@ -1,18 +0,0 @@
# i.MX8MQ M4 SoC series defconfig
# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX8MQ_M4
config SOC_SERIES
default "mimx8mq6_m4"
config NUM_IRQS
int
# must be >= the highest interrupt number used
default 127
source "soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4"
endif # SOC_SERIES_IMX8MQ_M4

14
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/Kconfig.series
View File

@@ -1,14 +0,0 @@
# i.MX8MQ M4 core series
# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMX8MQ_M4
bool "i.MX8MQ M4 Core Series"
select ARM
select CPU_CORTEX_M4
select SOC_FAMILY_IMX
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
help
Enable support for i.MX8MQ M4 MCU series

32
soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc
View File

@@ -1,32 +0,0 @@
# i.MX8MQ M4 SoC series
# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
# SPDX-License-Identifier: Apache-2.0
choice
prompt "i.MX8MQ M4 Selection"
depends on SOC_SERIES_IMX8MQ_M4
config SOC_MIMX8MQ6
bool "SOC_MIMX8MQ6"
select HAS_MCUX
select HAS_MCUX_CCM
select HAS_MCUX_RDC
select HAS_MCUX_IOMUXC
endchoice
if SOC_SERIES_IMX8MQ_M4
config SOC_PART_NUMBER_MIMX8MQ6DVAJZ
bool
config SOC_PART_NUMBER_IMX8MQ_M4
string
default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ
help
This string holds the full part number of the SoC. It is a hidden option
that you should not set directly. The part number selection choice defines
the default value for this string.
endif # SOC_SERIES_IMX8MQ_M4

65
soc/soc_legacy/arm/nxp_imx/rt/flexspi_rt11xx.c
View File

@@ -1,65 +0,0 @@
/*
* Copyright (c) 2023, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <fsl_clock.h>
#include <fsl_flexspi.h>
#include <soc.h>
#include <errno.h>
#include <zephyr/irq.h>
#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate)
{
clock_name_t root;
uint32_t root_rate;
FLEXSPI_Type *flexspi;
clock_root_t flexspi_clk;
clock_ip_name_t clk_gate;
uint32_t divider;
switch (clock_name) {
case IMX_CCM_FLEXSPI_CLK:
flexspi_clk = kCLOCK_Root_Flexspi1;
flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi));
clk_gate = kCLOCK_Flexspi1;
break;
case IMX_CCM_FLEXSPI2_CLK:
flexspi_clk = kCLOCK_Root_Flexspi2;
flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi2));
clk_gate = kCLOCK_Flexspi2;
break;
default:
return -ENOTSUP;
}
root = CLOCK_GetRootClockSource(flexspi_clk,
CLOCK_GetRootClockMux(flexspi_clk));
/* Get clock root frequency */
root_rate = CLOCK_GetFreq(root);
/* Select a divider based on root clock frequency. We round the
* divider up, so that the resulting clock frequency is lower than
* requested when we can't output the exact requested frequency
*/
divider = ((root_rate + (rate - 1)) / rate);
/* Cap divider to max value */
divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK);
while (FLEXSPI_GetBusIdleStatus(flexspi) == false) {
/* Spin */
}
FLEXSPI_Enable(flexspi, false);
CLOCK_DisableClock(clk_gate);
CLOCK_SetRootClockDiv(flexspi_clk, divider);
CLOCK_EnableClock(clk_gate);
FLEXSPI_Enable(flexspi, true);
FLEXSPI_SoftwareReset(flexspi);
return 0;
}