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hwmv2: soc: Port IMXRT family to HWMV2

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Port IMXRT family to HWMV2, including series:
- RT11XX
- RT10XX
- RT6XX

Not including RT5XX

Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
Co-authored-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Co-authored-by: David Leach <david.leach@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Co-authored-by: Emilio Benavente <emilio.benavente@nxp.com>

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder
2024-02-20 10:56:33 -06:00
committed by Carles Cufi
parent 28d4e41b1b
commit 417cff1e60
80 changed files with 1325 additions and 1508 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Kconfig.zephyr
View File

@@ -643,7 +643,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID
default "0x1c5f21b0" if SOC_SERIES_ESP32
default "0x621e937a" if SOC_NRF52833_QIAA
default "0xada52840" if SOC_NRF52840_QIAA
default "0x4fb2d5bd" if SOC_SERIES_IMX_RT
default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
default "0x2abc77ec" if SOC_SERIES_LPC55XXX
default "0xe48bff56" if SOC_SERIES_RP2XXX
default "0x68ed2b88" if SOC_SERIES_SAMD21

2
arch/arm/core/cortex_m/timing.c
View File

@@ -29,7 +29,7 @@
static inline uint64_t z_arm_dwt_freq_get(void)
{
#if defined(CONFIG_SOC_FAMILY_NRF) || \
defined(CONFIG_SOC_SERIES_IMX_RT6XX)
defined(CONFIG_SOC_SERIES_IMXRT6XX)
/*
* DWT frequency is taken directly from the
* System Core clock (CPU) frequency, if the

4
drivers/can/Kconfig.mcux
View File

@@ -42,8 +42,8 @@ config CAN_MAX_FILTER
int "Maximum number of concurrent active RX filters"
default 5
range 1 15 if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_KINETIS_K6X
range 1 13 if SOC_SERIES_IMX_RT && CAN_MCUX_FLEXCAN_FD
range 1 63 if SOC_SERIES_IMX_RT
range 1 13 if (SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX) && CAN_MCUX_FLEXCAN_FD
range 1 63 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
range 1 96 if SOC_SERIES_S32K3
range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W
range 1 64 if SOC_S32K142W || SOC_S32K144W

2
drivers/clock_control/clock_control_mcux_ccm.c
View File

@@ -353,7 +353,7 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev,
case IMX_CCM_FLEXSPI_CLK:
__fallthrough;
case IMX_CCM_FLEXSPI2_CLK:
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI)
/* The SOC is using the FlexSPI for XIP. Therefore,
* the FlexSPI itself must be managed within the function,
* which is SOC specific.

2
drivers/clock_control/clock_control_mcux_ccm_rev2.c
View File

@@ -173,7 +173,7 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev,
case IMX_CCM_FLEXSPI_CLK:
__fallthrough;
case IMX_CCM_FLEXSPI2_CLK:
#if defined(CONFIG_SOC_SERIES_IMX_RT11XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI)
#if defined(CONFIG_SOC_SERIES_IMXRT11XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI)
/* The SOC is using the FlexSPI for XIP. Therefore,
* the FlexSPI itself must be managed within the function,
* which is SOC specific.

4
drivers/ethernet/Kconfig.mcux
View File

@@ -94,8 +94,8 @@ if PTP_CLOCK_MCUX
config ETH_MCUX_PTP_CLOCK_SRC_HZ
int "Frequency of the clock source for the PTP timer"
default 50000000 if SOC_SERIES_KINETIS_K6X
default 50000000 if SOC_SERIES_IMX_RT10XX
default 24000000 if SOC_SERIES_IMX_RT11XX
default 50000000 if SOC_SERIES_IMXRT10XX
default 24000000 if SOC_SERIES_IMXRT11XX
help
Set the frequency in Hz sourced to the PTP timer.
If the value is set properly, the timer will be accurate.

18
drivers/ethernet/eth_mcux.c
View File

@@ -396,7 +396,7 @@ static void eth_mcux_phy_start(struct eth_context *context)
k_work_submit(&context->phy_work);
break;
#endif
#if defined(CONFIG_SOC_SERIES_IMX_RT)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
context->phy_state = eth_mcux_phy_state_initial;
#else
context->phy_state = eth_mcux_phy_state_reset;
@@ -453,7 +453,7 @@ static void eth_mcux_phy_event(struct eth_context *context)
uint32_t status;
#endif
bool link_up;
#if defined(CONFIG_SOC_SERIES_IMX_RT)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
status_t res;
uint16_t ctrl2;
#endif
@@ -466,7 +466,7 @@ static void eth_mcux_phy_event(struct eth_context *context)
#endif
switch (context->phy_state) {
case eth_mcux_phy_state_initial:
#if defined(CONFIG_SOC_SERIES_IMX_RT)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
ENET_DisableInterrupts(context->base, ENET_EIR_MII_MASK);
res = PHY_Read(context->phy_handle, PHY_CONTROL2_REG, &ctrl2);
ENET_EnableInterrupts(context->base, ENET_EIR_MII_MASK);
@@ -481,7 +481,7 @@ static void eth_mcux_phy_event(struct eth_context *context)
ctrl2);
}
context->phy_state = eth_mcux_phy_state_reset;
#endif /* CONFIG_SOC_SERIES_IMX_RT */
#endif
#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
/*
* When the iface is available proceed with the eth link setup,
@@ -633,7 +633,7 @@ static void eth_mcux_delayed_phy_work(struct k_work *item)
static void eth_mcux_phy_setup(struct eth_context *context)
{
#if defined(CONFIG_SOC_SERIES_IMX_RT)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
status_t res;
uint16_t oms_override;
@@ -1024,14 +1024,14 @@ static void eth_mcux_init(const struct device *dev)
context->phy_state = eth_mcux_phy_state_initial;
context->phy_handle->ops = &phyksz8081_ops;
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
sys_clock = CLOCK_GetFreq(kCLOCK_IpgClk);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
sys_clock = CLOCK_GetFreq(kCLOCK_EnetPll1Clk);
#endif
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
sys_clock = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus);
#else
sys_clock = CLOCK_GetFreq(kCLOCK_CoreSysClk);
@@ -1391,9 +1391,9 @@ static void eth_mcux_err_isr(const struct device *dev)
}
#endif
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX)
#define ETH_MCUX_UNIQUE_ID (OCOTP->CFG1 ^ OCOTP->CFG2)
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
#define ETH_MCUX_UNIQUE_ID (OCOTP->FUSEN[40].FUSE)
#elif defined(CONFIG_SOC_SERIES_KINETIS_K6X)
#define ETH_MCUX_UNIQUE_ID (SIM->UIDH ^ SIM->UIDMH ^ SIM->UIDML ^ SIM->UIDL)

4
drivers/ethernet/eth_nxp_enet.c
View File

@@ -772,9 +772,9 @@ static const struct ethernet_api api_funcs = {
#define FREESCALE_OUI_B1 0x04
#define FREESCALE_OUI_B2 0x9f
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX)
#define ETH_NXP_ENET_UNIQUE_ID (OCOTP->CFG1 ^ OCOTP->CFG2)
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
#define ETH_NXP_ENET_UNIQUE_ID (OCOTP->FUSEN[40].FUSE)
#elif defined(CONFIG_SOC_SERIES_KINETIS_K6X)
#define ETH_NXP_ENET_UNIQUE_ID (SIM->UIDH ^ SIM->UIDMH ^ SIM->UIDML ^ SIM->UIDL)

6
drivers/gpio/gpio_mcux_igpio.c
View File

@@ -72,7 +72,7 @@ static int mcux_igpio_configure(const struct device *dev,
(volatile uint32_t *)config->pin_muxes[cfg_idx].config_register;
uint32_t reg = *gpio_cfg_reg;
#ifdef CONFIG_SOC_SERIES_IMX_RT10XX
#ifdef CONFIG_SOC_SERIES_IMXRT10XX
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
@@ -92,7 +92,7 @@ static int mcux_igpio_configure(const struct device *dev,
/* Set pin to keeper */
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
}
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
if (config->pin_muxes[pin].pue_mux) {
/* PUE type register layout (GPIO_AD pins) */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
@@ -184,7 +184,7 @@ static int mcux_igpio_configure(const struct device *dev,
/* Set pin to highz */
reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
}
#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */
#endif /* CONFIG_SOC_SERIES_IMXRT10XX */
memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux));
/* cfg register will be set by pinctrl_configure_pins */

2
drivers/hwinfo/Kconfig
View File

@@ -109,7 +109,7 @@ config HWINFO_MCUX_SYSCON
config HWINFO_IMXRT
bool "NXP i.mx RT device ID"
default y
depends on SOC_SERIES_IMX_RT
depends on SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
help
Enable NXP i.mx RT hwinfo driver.

2
drivers/hwinfo/hwinfo_imxrt.c
View File

@@ -17,7 +17,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct imxrt_uid dev_id;
#ifdef CONFIG_SOC_SERIES_IMX_RT11XX
#ifdef CONFIG_SOC_SERIES_IMXRT11XX
dev_id.id[0] = sys_cpu_to_be32(OCOTP->FUSEN[17].FUSE);
dev_id.id[1] = sys_cpu_to_be32(OCOTP->FUSEN[16].FUSE);
#else

4
drivers/i2s/i2s_mcux_sai.c
View File

@@ -1148,13 +1148,13 @@ static void audio_clock_settings(const struct device *dev)
imxrt_audio_codec_pll_init(clock_name, dev_cfg->clk_src,
dev_cfg->clk_pre_div, dev_cfg->clk_src_div);
#ifdef CONFIG_SOC_SERIES_IMX_RT11XX
#ifdef CONFIG_SOC_SERIES_IMXRT11XX
audioPllConfig.loopDivider = dev_cfg->pll_lp;
audioPllConfig.postDivider = dev_cfg->pll_pd;
audioPllConfig.numerator = dev_cfg->pll_num;
audioPllConfig.denominator = dev_cfg->pll_den;
audioPllConfig.ssEnable = false;
#elif defined CONFIG_SOC_SERIES_IMX_RT10XX
#elif defined CONFIG_SOC_SERIES_IMXRT10XX
audioPllConfig.src = dev_cfg->pll_src;
audioPllConfig.loopDivider = dev_cfg->pll_lp;
audioPllConfig.postDivider = dev_cfg->pll_pd;

12
drivers/pinctrl/pinctrl_imx.c
View File

@@ -19,7 +19,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uint32_t input_daisy = pins[i].pinmux.input_daisy;
uint32_t config_register = pins[i].pinmux.config_register;
uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
volatile uint32_t *gpr_register =
(volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register);
if (gpr_register) {
@@ -65,17 +65,17 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
static int imx_pinctrl_init(void)
{
#ifdef CONFIG_SOC_SERIES_IMX_RT
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
CLOCK_EnableClock(kCLOCK_Iomuxc);
#ifdef CONFIG_SOC_SERIES_IMX_RT10XX
#ifdef CONFIG_SOC_SERIES_IMXRT10XX
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
CLOCK_EnableClock(kCLOCK_IomuxcGpr);
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */
#endif /* CONFIG_SOC_SERIES_IMXRT10XX */
#elif defined(CONFIG_SOC_MIMX8MQ6)
CLOCK_EnableClock(kCLOCK_Iomux);
#endif /* CONFIG_SOC_SERIES_IMX_RT */
#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */
return 0;
}

4
drivers/serial/uart_mcux_flexcomm.c
View File

@@ -813,7 +813,7 @@ static void mcux_flexcomm_uart_dma_rx_callback(const struct device *dma_device,
data->rx_data.offset = 0;
}
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX)
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMXRT6XX)
/*
* This functions calculates the inputmux connection value
* needed by INPUTMUX_EnableSignal to allow the UART's DMA
@@ -902,7 +902,7 @@ static int flexcomm_uart_async_init(const struct device *dev)
USART_EnableRxDMA(config->base, false);
/* Route DMA requests */
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX)
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMXRT6XX)
/* RT 3 digit uses input mux to route DMA requests from
* the UART peripheral to a hardware designated DMA channel
*/

4
drivers/usb/device/usb_dc_mcux.c
View File

@@ -77,7 +77,7 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported");
/* Controller ID is for HAL usage */
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || \
defined(CONFIG_SOC_SERIES_IMX_RT6XX) || \
defined(CONFIG_SOC_SERIES_IMXRT6XX) || \
defined(CONFIG_SOC_LPC55S28) || \
defined(CONFIG_SOC_LPC55S16)
#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0
@@ -89,7 +89,7 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported");
#elif DT_NODE_HAS_STATUS(DT_NODELABEL(usbfs), okay)
#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0
#endif /* LPC55s69 */
#elif defined(CONFIG_SOC_SERIES_IMX_RT)
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay)
#define CONTROLLER_ID kUSB_ControllerEhci0
#elif DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay)

2
modules/Kconfig.mcux
View File

@@ -6,7 +6,7 @@
config HAS_MCUX
bool
depends on SOC_FAMILY_KINETIS || SOC_FAMILY_IMX || SOC_FAMILY_LPC || \
SOC_FAMILY_NXP_ADSP || SOC_FAMILY_NXP_S32
SOC_FAMILY_NXP_ADSP || SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT
if HAS_MCUX

4
modules/hal_nxp/CMakeLists.txt
View File

@@ -15,4 +15,8 @@ if(CONFIG_HAS_MCUX OR CONFIG_HAS_IMX_HAL OR CONFIG_HAS_NXP_S32_HAL)
zephyr_compile_definitions_ifdef(CONFIG_CAN_MCUX_FLEXCAN
FLEXCAN_WAIT_TIMEOUT=${CONFIG_CAN_MCUX_FLEXCAN_WAIT_TIMEOUT})
zephyr_compile_definitions_ifdef(CONFIG_ENTROPY_MCUX_CAAM CACHE_MODE_WRITE_THROUGH)
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER DATA_SECTION_IS_CACHEABLE=1)
endif()

42
soc/nxp/imxrt/CMakeLists.txt Normal file
View File

@@ -0,0 +1,42 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(${SOC_SERIES})
zephyr_include_directories(.)
zephyr_include_directories(${SOC_SERIES})
zephyr_linker_sources_ifdef(CONFIG_NXP_IMXRT_BOOT_HEADER
ROM_START SORT_KEY 0 boot_header.ld)
if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX)
if(CONFIG_DEVICE_CONFIGURATION_DATA)
set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data")
endif()
zephyr_sources(mpu_regions.c)
zephyr_linker_section_configure(
SECTION .rom_start
INPUT ".boot_hdr.conf"
OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET}
KEEP
PRIO 10
)
zephyr_linker_section_configure(
SECTION .rom_start
INPUT ".boot_hdr.ivt"
".boot_hdr.data"
${boot_hdr_dcd_data_section}
OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET}
KEEP
PRIO 11
)
zephyr_compile_definitions(XIP_EXTERNAL_FLASH)
endif()
if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMX_RT5XX)
zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld)
endif()
if(CONFIG_MEMC)
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc)
endif()

164
soc/nxp/imxrt/Kconfig Normal file
View File

@@ -0,0 +1,164 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_NXP_IMXRT
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
select HAS_PM
if SOC_FAMILY_NXP_IMXRT
# Source series Kconfig files first, so SOCs
# can override the defaults given here
rsource "*/Kconfig"
# Used for default value in FLASH_MCUX_FLEXSPI_XIP
DT_CHOSEN_Z_FLASH := zephyr,flash
DT_COMPAT_FLEXSPI := nxp,imx-flexspi
# Macros to shorten Kconfig definitions
DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
config FLASH_MCUX_FLEXSPI_XIP
bool "MCUX FlexSPI flash access with xip"
default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
select XIP
help
Allows for the soc to safely initialize the clocks for the
FlexSpi when planning to execute code in FlexSpi Memory.
# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
# should be set elsewhere, since the determination of which SOC core
# requires the boot header is SOC specific.
config NXP_IMXRT_BOOT_HEADER
bool "Boot header"
default y
depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX)
help
Enable data structures required by the boot ROM to boot the
application from an external flash device.
if NXP_IMXRT_BOOT_HEADER
choice BOOT_DEVICE
prompt "Boot device"
default BOOT_FLEXSPI_NOR
config BOOT_FLEXSPI_NOR
bool "FlexSPI serial NOR"
depends on HAS_MCUX_FLEXSPI
config BOOT_FLEXSPI_NAND
bool "FlexSPI serial NAND"
depends on HAS_MCUX_FLEXSPI
config BOOT_SEMC_NOR
bool "SEMC parallel NOR"
depends on HAS_MCUX_SEMC
config BOOT_SEMC_NAND
bool "SEMC parallel NAND"
depends on HAS_MCUX_SEMC
endchoice # BOOT_DEVICE
config FLEXSPI_CONFIG_BLOCK_OFFSET
hex "FlexSPI config block offset"
default 0x400 if SOC_SERIES_IMX_RT5XX || SOC_SERIES_IMXRT6XX
default 0x0 if BOOT_FLEXSPI_NOR
help
FlexSPI configuration block consists of parameters regarding specific
flash devices including read command sequence, quad mode enablement
sequence (optional), etc. The boot ROM expects FlexSPI configuration
parameter to be presented in serial nor flash.
config IMAGE_VECTOR_TABLE_OFFSET
hex "Image vector table offset"
default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
help
The Image Vector Table (IVT) provides the boot ROM with pointers to
the application entry point and device configuration data. The boot
ROM requires a fixed IVT offset for each type of boot device.
config DEVICE_CONFIGURATION_DATA
bool "Device configuration data"
help
Device configuration data (DCD) provides a sequence of commands to
the boot ROM to initialize components such as an SDRAM. This is
useful if your application expects components like SDRAM to be
initialized at boot time.
endif # NXP_IMXRT_BOOT_HEADER
config NXP_IMX_EXTERNAL_SDRAM
bool "Allow access to external SDRAM region"
help
Enable access to external SDRAM region managed by the SEMC. This
setting should be enabled when the application uses SDRAM, or
an MPU region will be defined to disable cached access to the
SDRAM memory space.
config NXP_IMX_RT_ROM_RAMLOADER
depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMXRT_BOOT_HEADER
# Required so that debugger will load image to correct offset
select BUILD_OUTPUT_HEX
bool "Create output image that IMX RT ROM can load from FlexSPI to ram"
help
Builds an output image that the IMX RT BootROM can load from the
FlexSPI boot device into RAM region. The image will be loaded
from FLEXSPI into the region specified by `zephyr,flash` node.
# Setup LMA adjustment if using the RAMLOADER feature of ROM
FLASH_CHOSEN := zephyr,flash
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1)
config BUILD_OUTPUT_ADJUST_LMA
default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER
config SECOND_CORE_MCUX
bool "Dual core operation on the RT11xx series"
depends on SOC_SERIES_IMXRT11XX
help
Indicates the second core will be enabled, and the part will run
in dual core mode. Enables dual core operation on the RT11xx series,
by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU.
The M4 image will be loaded from flash into RAM based off a
generated header specifying the VMA and LMA of each memory section
to load
config FLEXSPI_CONFIG_BLOCK_OFFSET
hex
default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
config PM_MCUX_GPC
bool "MCUX general power controller driver"
config PM_MCUX_DCDC
bool "MCUX dcdc converter module driver"
config PM_MCUX_PMU
bool "MCUX power management unit driver"
config DCDC_VALUE
hex "DCDC value for VDD_SOC"
config INIT_ARM_PLL
bool "Initialize ARM PLL"
config INIT_VIDEO_PLL
bool "Initialize Video PLL"
config INIT_ENET_PLL
bool
help
If y, the Ethernet PLL is initialized. Always enabled on e.g.
MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
for MIMXRT1021").
endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
endif # SOC_FAMILY_NXP_IMXRT

90
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.series → soc/nxp/imxrt/Kconfig.defconfig
View File

@@ -1,12 +1,17 @@
# i.MX RT series
# Copyright (c) 2017-2021, NXP
# Copyright 2017-2024 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX_RT
if SOC_FAMILY_NXP_IMXRT
config SOC_SERIES
default "rt"
# Source series Kconfig files first, so SOCs
# can override the defaults given here
rsource "*/Kconfig.defconfig"
if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
config SERIAL_INIT_PRIORITY
default 55 if SERIAL
depends on SERIAL
config ROM_START_OFFSET
default 0x400 if BOOTLOADER_MCUBOOT
@@ -24,19 +29,6 @@ config LOG_BACKEND_SWO_FREQ_HZ
default 7500000
depends on LOG_BACKEND_SWO
if FLASH_MCUX_FLEXSPI_XIP
# Avoid RWW hazards by defaulting logging to disabled
choice FLASH_LOG_LEVEL_CHOICE
default FLASH_LOG_LEVEL_OFF
endchoice
choice MEMC_LOG_LEVEL_CHOICE
default MEMC_LOG_LEVEL_OFF
endchoice
endif
# set the tick per sec as a divider of the GPT clock source
config SYS_CLOCK_TICKS_PER_SEC
default 4096 if MCUX_GPT_TIMER
@@ -44,7 +36,7 @@ config SYS_CLOCK_TICKS_PER_SEC
DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMX_RT10XX && CORTEX_M_SYSTICK
default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMXRT10XX && CORTEX_M_SYSTICK
default 32768 if MCUX_GPT_TIMER
# Disable systick if using MCUX_GPT_TIMER, as they will conflict
@@ -53,13 +45,13 @@ config CORTEX_M_SYSTICK
config PM_MCUX_GPC
default y if HAS_MCUX_GPC
depends on SOC_SERIES_IMX_RT11XX && PM
depends on SOC_SERIES_IMXRT11XX && PM
# Don't allow SOC to sleep after tests complete when PM is enabled
config ZTEST_NO_YIELD
default y if (ZTEST && PM)
if SOC_SERIES_IMX_RT10XX && PM
if SOC_SERIES_IMXRT10XX && PM
config CODE_DATA_RELOCATION
default y
@@ -73,7 +65,7 @@ config PM_MCUX_DCDC
config PM_MCUX_PMU
default y if HAS_MCUX_PMU
endif # SOC_SERIES_IMX_RT10XX && PM
endif # SOC_SERIES_IMXRT10XX && PM
if ETH_NXP_ENET
@@ -82,23 +74,6 @@ config SYSTEM_WORKQUEUE_STACK_SIZE
endif # ETH_NXP_ENET
DT_CHOSEN_Z_FLASH := zephyr,flash
DT_COMPAT_FLEXSPI := nxp,imx-flexspi
DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
if $(DT_FLASH_PARENT_IS_FLEXSPI)
config FLASH_SIZE
default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
if $(DT_FLASH_HAS_SIZE_PROP)
config MEMC
default y
@@ -141,6 +116,37 @@ endif # MBEDTLS
config CACHE_MANAGEMENT
default y if CPU_CORTEX_M7
source "soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*"
endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
endif # SOC_SERIES_IMX_RT
# Logic to set flash size for all IMXRT parts
DT_CHOSEN_Z_FLASH := zephyr,flash
DT_COMPAT_FLEXSPI := nxp,imx-flexspi
DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
if $(DT_FLASH_PARENT_IS_FLEXSPI)
config FLASH_SIZE
default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
if $(DT_FLASH_HAS_SIZE_PROP)
if FLASH_MCUX_FLEXSPI_XIP
# Avoid RWW hazards by defaulting logging to disabled
choice FLASH_LOG_LEVEL_CHOICE
default FLASH_LOG_LEVEL_OFF
endchoice
choice MEMC_LOG_LEVEL_CHOICE
default MEMC_LOG_LEVEL_OFF
endchoice
endif
endif # SOC_FAMILY_NXP_IMXRT

10
soc/nxp/imxrt/Kconfig.soc Normal file
View File

@@ -0,0 +1,10 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_NXP_IMXRT
bool
config SOC_FAMILY
default "nxp_imxrt" if SOC_FAMILY_NXP_IMXRT
rsource "*/Kconfig.soc"

21
soc/nxp/imxrt/boot_header.ld Normal file
View File

@@ -0,0 +1,21 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
KEEP(*(.boot_hdr.conf))
#endif
#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMX_RT5XX)
KEEP(*(.flash_conf))
#endif
. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
KEEP(*(.boot_hdr.ivt))
#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
KEEP(*(.boot_hdr.data))
#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
KEEP(*(.boot_hdr.dcd_data))
#endif /* CONFIG_DEVICE_CONFIGURATION_DATA */
#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */

2
soc/soc_legacy/arm/nxp_imx/rt/flexspi_nor_config.h → soc/nxp/imxrt/flexspi_nor_config.h
View File

@@ -91,7 +91,7 @@ enum {
kFlexSpiSerialClk_133MHz = 7,
};
#elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \
defined(CONFIG_SOC_SERIES_IMX_RT11XX)
defined(CONFIG_SOC_SERIES_IMXRT11XX)
enum {
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,

27
soc/nxp/imxrt/imxrt10xx/CMakeLists.txt Normal file
View File

@@ -0,0 +1,27 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_sources(soc.c)
if(CONFIG_PM)
zephyr_sources(power.c)
zephyr_code_relocate(FILES power.c LOCATION ITCM_TEXT)
if(CONFIG_SOC_MIMXRT1064)
zephyr_sources(lpm_rt1064.c)
zephyr_code_relocate(FILES lpm_rt1064 LOCATION ITCM_TEXT)
endif()
endif()
if(CONFIG_MEMC_MCUX_FLEXSPI)
zephyr_sources(flexspi.c)
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flexspi.c LOCATION ITCM_TEXT)
endif()
endif()
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

150
soc/nxp/imxrt/imxrt10xx/Kconfig Normal file
View File

@@ -0,0 +1,150 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMXRT10XX
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select PLATFORM_SPECIFIC_INIT
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select ARM
select CLOCK_CONTROL
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR if !SOC_MIMXRT1042
select HAS_MCUX_CCM if !SOC_MIMXRT1042
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C if !SOC_MIMXRT1042
select HAS_MCUX_LPSPI if !SOC_MIMXRT1042
select HAS_MCUX_LPUART if !SOC_MIMXRT1042
select HAS_MCUX_GPT if !SOC_MIMXRT1042
select HAS_MCUX_TRNG if !SOC_MIMXRT1042
select HAS_MCUX_EDMA
select HAS_MCUX_GPC
select HAS_MCUX_IOMUXC
select HAS_MCUX_PMU
select HAS_MCUX_DCDC
select HAS_MCUX_USB_EHCI
select HAS_SWO
config SOC_MIMXRT1011
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select INIT_ENET_PLL
config SOC_MIMXRT1015
select CPU_HAS_FPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ENET_PLL
config SOC_MIMXRT1021
select HAS_MCUX_ENET
select HAS_MCUX_SEMC
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ENET_PLL
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_FLEXCAN
select HAS_MCUX_PWM
config SOC_MIMXRT1024
select HAS_MCUX_ENET
select HAS_MCUX_SEMC
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ENET_PLL
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_FLEXCAN
select HAS_MCUX_SRC
config SOC_MIMXRT1042
select HAS_MCUX_SEMC
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
config SOC_MIMXRT1051
select HAS_MCUX_ENET
select HAS_MCUX_SEMC
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_FLEXCAN
config SOC_MIMXRT1052
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
select HAS_MCUX_SEMC
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_FLEXCAN
select HAS_MCUX_PWM
select HAS_MCUX_SRC
select HAS_MCUX_XBARA
config SOC_MIMXRT1061
select HAS_MCUX_ENET
select HAS_MCUX_SEMC
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_FLEXCAN
config SOC_MIMXRT1062
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
select HAS_MCUX_PWM
select HAS_MCUX_QTMR
select HAS_MCUX_SEMC
select HAS_MCUX_SNVS
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_FLEXCAN
select HAS_MCUX_I2S
select HAS_MCUX_ADC_ETC
select HAS_MCUX_SRC
select HAS_MCUX_XBARA
config SOC_MIMXRT1064
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
select HAS_MCUX_PWM
select HAS_MCUX_QTMR
select HAS_MCUX_SEMC
select HAS_MCUX_SNVS
select HAS_MCUX_SRC
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_FLEXCAN
select HAS_SWO

28
soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMXRT10XX
config NUM_IRQS
default 80 if SOC_MIMXRT1011
default 142 if SOC_MIMXRT1015 || \
SOC_MIMXRT1021 || \
SOC_MIMXRT1024
default 157 if SOC_MIMXRT1042
default 160 if SOC_MIMXRT1052 || \
SOC_MIMXRT1062 || \
SOC_MIMXRT1064
config DCDC_VALUE
default 0x12 if SOC_MIMXRT1011 || \
SOC_MIMXRT1015 || \
SOC_MIMXRT1021 || \
SOC_MIMXRT1024
default 0x13
config GPIO
default y
endif # SOC_SERIES_IMXRT10XX

238
soc/nxp/imxrt/imxrt10xx/Kconfig.soc Normal file
View File

@@ -0,0 +1,238 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMXRT10XX
bool
select SOC_FAMILY_NXP_IMXRT
config SOC_SERIES
default "imxrt10xx" if SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1011
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1015
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1021
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1024
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1042
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1051
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1052
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1061
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1062
bool
select SOC_SERIES_IMXRT10XX
config SOC_MIMXRT1064
bool
select SOC_SERIES_IMXRT10XX
config SOC
default "mimxrt1011" if SOC_MIMXRT1011
default "mimxrt1015" if SOC_MIMXRT1015
default "mimxrt1021" if SOC_MIMXRT1021
default "mimxrt1024" if SOC_MIMXRT1024
default "mimxrt1042" if SOC_MIMXRT1042
default "mimxrt1051" if SOC_MIMXRT1051
default "mimxrt1052" if SOC_MIMXRT1052
default "mimxrt1061" if SOC_MIMXRT1061
default "mimxrt1062" if SOC_MIMXRT1062
default "mimxrt1064" if SOC_MIMXRT1064
config SOC_PART_NUMBER_MIMXRT1011CAE4A
bool
select SOC_MIMXRT1011
config SOC_PART_NUMBER_MIMXRT1011DAE5A
bool
select SOC_MIMXRT1011
config SOC_PART_NUMBER_MIMXRT1015CAF4A
bool
select SOC_MIMXRT1015
config SOC_PART_NUMBER_MIMXRT1015DAF5A
bool
select SOC_MIMXRT1015
config SOC_PART_NUMBER_MIMXRT1021CAF4A
bool
select SOC_MIMXRT1021
config SOC_PART_NUMBER_MIMXRT1021CAG4A
bool
select SOC_MIMXRT1021
config SOC_PART_NUMBER_MIMXRT1021DAF5A
bool
select SOC_MIMXRT1021
config SOC_PART_NUMBER_MIMXRT1021DAG5A
bool
select SOC_MIMXRT1021
config SOC_PART_NUMBER_MIMXRT1024CAG4A
bool
select SOC_MIMXRT1024
config SOC_PART_NUMBER_MIMXRT1024DAG5A
bool
select SOC_MIMXRT1024
config SOC_PART_NUMBER_MIMXRT1041DFP6B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1041DJM6B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1041XFP5B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1041XJM5B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1042DFP6B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1042DJM6B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1042XFP5B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1042XJM5B
bool
select SOC_MIMXRT1042
config SOC_PART_NUMBER_MIMXRT1051CVL5A
bool
select SOC_MIMXRT1051
config SOC_PART_NUMBER_MIMXRT1051DVL6A
bool
select SOC_MIMXRT1051
config SOC_PART_NUMBER_MIMXRT1052CVJ5B
bool
select SOC_MIMXRT1052
config SOC_PART_NUMBER_MIMXRT1052CVL5A
bool
select SOC_MIMXRT1052
config SOC_PART_NUMBER_MIMXRT1052CVL5B
bool
select SOC_MIMXRT1052
config SOC_PART_NUMBER_MIMXRT1052DVJ6B
bool
select SOC_MIMXRT1052
config SOC_PART_NUMBER_MIMXRT1052DVL6A
bool
select SOC_MIMXRT1052
config SOC_PART_NUMBER_MIMXRT1052DVL6B
bool
select SOC_MIMXRT1052
config SOC_PART_NUMBER_MIMXRT1061CVL5A
bool
select SOC_MIMXRT1061
config SOC_PART_NUMBER_MIMXRT1061DVL6A
bool
select SOC_MIMXRT1061
config SOC_PART_NUMBER_MIMXRT1062CVJ5A
bool
select SOC_MIMXRT1062
config SOC_PART_NUMBER_MIMXRT1062CVJ5B
bool
select SOC_MIMXRT1062
config SOC_PART_NUMBER_MIMXRT1062CVL5A
bool
select SOC_MIMXRT1062
config SOC_PART_NUMBER_MIMXRT1062DVJ6A
bool
select SOC_MIMXRT1062
config SOC_PART_NUMBER_MIMXRT1062DVL6A
bool
select SOC_MIMXRT1062
config SOC_PART_NUMBER_MIMXRT1064CVL5A
bool
select SOC_MIMXRT1064
config SOC_PART_NUMBER_MIMXRT1064DVL6A
bool
select SOC_MIMXRT1064
config SOC_PART_NUMBER
default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A
default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A
default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A
default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A
default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A
default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A
default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A
default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A
default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A
default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B
default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B
default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B
default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B
default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B
default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B
default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B
default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B
default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A
default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B
default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A
default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B
default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A
default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A
default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A
default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B
default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A
default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A
default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A
default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A
default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A

0
soc/soc_legacy/arm/nxp_imx/rt/flexspi_rt10xx.c → soc/nxp/imxrt/imxrt10xx/flexspi.c
View File

5
soc/soc_legacy/arm/nxp_imx/rt/linker.ld → soc/nxp/imxrt/imxrt10xx/linker.ld
View File

@@ -4,15 +4,18 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/devicetree.h>
#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
MEMORY
{
#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0))
#endif
}
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>

20
soc/soc_legacy/arm/nxp_imx/rt/lpm_rt1064.c → soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c
View File

@@ -8,7 +8,7 @@
*/
#include <zephyr/init.h>
#include <power_rt10xx.h>
#include <power.h>
#include <zephyr/kernel.h>
#include <fsl_clock.h>
@@ -117,7 +117,7 @@ static void clock_init_usb1_pll(const clock_usb_pll_config_t *config)
static void flexspi_enter_critical(void)
{
#if CONFIG_CODE_FLEXSPI2
#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash)))
/* Wait for flexspi to be inactive, and gate the clock */
while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&
(FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {
@@ -126,7 +126,9 @@ static void flexspi_enter_critical(void)
/* Disable clock gate of flexspi2. */
CCM->CCGR7 &= (~CCM_CCGR7_CG1_MASK);
#elif CONFIG_CODE_FLEXSPI
#endif
#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash)))
/* Wait for flexspi to be inactive, and gate the clock */
while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&
(FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {
@@ -140,7 +142,7 @@ static void flexspi_enter_critical(void)
static void flexspi_exit_critical(void)
{
#if CONFIG_CODE_FLEXSPI2
#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash)))
/* Enable clock gate of flexspi2. */
CCM->CCGR7 |= (CCM_CCGR7_CG1_MASK);
@@ -151,7 +153,7 @@ static void flexspi_exit_critical(void)
while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&
(FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {
}
#elif CONFIG_CODE_FLEXSPI
#elif DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash)))
/* Enable clock of flexspi. */
CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
@@ -209,10 +211,10 @@ void clock_full_power(void)
#endif
/* Set Flexspi divider before increasing frequency of PLL3 PDF0. */
#if CONFIG_CODE_FLEXSPI
#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash)))
clock_set_div(kCLOCK_FlexspiDiv, flexspi_div);
clock_set_mux(kCLOCK_FlexspiMux, 3);
#elif CONFIG_CODE_FLEXSPI2
#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash)))
clock_set_div(kCLOCK_Flexspi2Div, flexspi_div);
clock_set_mux(kCLOCK_Flexspi2Mux, 1);
#endif
@@ -255,11 +257,11 @@ void clock_low_power(void)
CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE_MASK;
CCM_ANALOG->PFD_480_CLR = CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK;
/* Change flexspi to use PLL3 PFD0 with no divisor (24M flexspi clock) */
#if CONFIG_CODE_FLEXSPI
#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash)))
clock_set_div(kCLOCK_FlexspiDiv, 0);
/* FLEXSPI1 mux to PLL3 PFD0 BYPASS */
clock_set_mux(kCLOCK_FlexspiMux, 3);
#elif CONFIG_CODE_FLEXSPI2
#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash)))
clock_set_div(kCLOCK_Flexspi2Div, 0);
/* FLEXSPI2 mux to PLL3 PFD0 BYPASS */
clock_set_mux(kCLOCK_Flexspi2Mux, 1);

0
soc/soc_legacy/arm/nxp_imx/rt/pinctrl_rt10xx.h → soc/nxp/imxrt/imxrt10xx/pinctrl_soc.h
View File

2
soc/soc_legacy/arm/nxp_imx/rt/power_rt10xx.c → soc/nxp/imxrt/imxrt10xx/power.c
View File

@@ -16,7 +16,7 @@
#include <zephyr/logging/log.h>
#include <zephyr/sys/barrier.h>
#include "power_rt10xx.h"
#include "power.h"
LOG_MODULE_REGISTER(soc_power, CONFIG_SOC_LOG_LEVEL);

0
soc/soc_legacy/arm/nxp_imx/rt/power_rt10xx.h → soc/nxp/imxrt/imxrt10xx/power.h
View File

4
soc/soc_legacy/arm/nxp_imx/rt/soc_rt10xx.c → soc/nxp/imxrt/imxrt10xx/soc.c
View File

@@ -12,7 +12,7 @@
#include <zephyr/linker/linker-defs.h>
#include <zephyr/cache.h>
#include <fsl_clock.h>
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
#include <fsl_flexspi_nor_boot.h>
#endif
#include <zephyr/dt-bindings/clock/imx_ccm.h>
@@ -93,7 +93,7 @@ const clock_video_pll_config_t videoPllConfig = {
};
#endif
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
const __imx_boot_data_section BOOT_DATA_T boot_data = {
#ifdef CONFIG_XIP
.start = CONFIG_FLASH_BASE_ADDRESS,

3
soc/soc_legacy/arm/nxp_imx/rt/soc.h → soc/nxp/imxrt/imxrt10xx/soc.h
View File

@@ -32,6 +32,9 @@ void imxrt_pre_init_display_interface(void);
void imxrt_post_init_display_interface(void);
#endif
void flexspi_clock_set_div(uint32_t value);
uint32_t flexspi_clock_get_freq(void);
#ifdef CONFIG_MEMC
uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate);
#endif

19
soc/nxp/imxrt/imxrt11xx/CMakeLists.txt Normal file
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@@ -0,0 +1,19 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_sources(soc.c)
zephyr_sources_ifdef(CONFIG_PM power.c)
zephyr_include_directories(.)
if(CONFIG_MEMC_MCUX_FLEXSPI)
zephyr_sources(flexspi.c)
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flexspi.c LOCATION ITCM_TEXT)
endif()
endif()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

74
soc/nxp/imxrt/imxrt11xx/Kconfig Normal file
View File

@@ -0,0 +1,74 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMXRT11XX
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select CPU_CORTEX_M_HAS_DWT
select PLATFORM_SPECIFIC_INIT
select ARM
select CLOCK_CONTROL
select HAS_MCUX_CACHE
select HAS_MCUX
select HAS_MCUX_SEMC
select HAS_MCUX_CCM_REV2
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPADC
select HAS_MCUX_LPUART
select HAS_MCUX_ELCDIF
select HAS_MCUX_MIPI_DSI
select HAS_MCUX_GPT
select HAS_MCUX_FLEXSPI
select HAS_MCUX_FLEXCAN
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select INIT_VIDEO_PLL
select HAS_MCUX_EDMA
select CPU_HAS_ICACHE if CPU_CORTEX_M7
select CPU_HAS_DCACHE if CPU_CORTEX_M7
select CPU_HAS_FPU_DOUBLE_PRECISION
select BYPASS_LDO_LPSR
select ADJUST_LDO
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
select HAS_MCUX_GPC
select HAS_MCUX_I2S
select HAS_MCUX_USB_EHCI
select HAS_MCUX_ACMP
select HAS_MCUX_SRC_V2
select HAS_MCUX_IOMUXC
select HAS_MCUX_XBARA
select HAS_SWO
config SOC_MIMXRT1176_CM4
select CPU_CORTEX_M4
config SOC_MIMXRT1176_CM7
select CPU_CORTEX_M7
config SOC_MIMXRT1166_CM4
select CPU_CORTEX_M4
config SOC_MIMXRT1166_CM7
select CPU_CORTEX_M7
if SOC_SERIES_IMXRT11XX
config MCUX_CORE_SUFFIX
default "_cm7" if SOC_MIMXRT1176_CM7 || SOC_MIMXRT1166_CM7
default "_cm4" if SOC_MIMXRT1176_CM4 || SOC_MIMXRT1166_CM4
config BYPASS_LDO_LPSR
bool "Bypass LDO lpsr"
config ADJUST_LDO
bool "Adjust LDO setting"
config ADJUST_DCDC
bool "Adjust internal DCDC output"
endif # SOC_SERIES_IMXRT11XX

35
soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig Normal file
View File

@@ -0,0 +1,35 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMXRT11XX
config NUM_IRQS
default 218
config GPIO
default y
if CORTEX_M_SYSTICK
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 996000000 if SOC_MIMXRT1176_CM7
default 600000000 if SOC_MIMXRT1166_CM7
default 400000000 if SOC_MIMXRT1176_CM4
default 240000000 if SOC_MIMXRT1166_CM4
endif # CORTEX_M_SYSTICK
config DCDC_VALUE
default 0x13
config FLEXSPI_CONFIG_BLOCK_OFFSET
default 0x400 if BOOT_FLEXSPI_NOR
if SECOND_CORE_MCUX
# RT Boot header is only needed on primary core
config NXP_IMXRT_BOOT_HEADER
depends on CPU_CORTEX_M7
endif
endif

95
soc/nxp/imxrt/imxrt11xx/Kconfig.soc Normal file
View File

@@ -0,0 +1,95 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMXRT11XX
bool
select SOC_FAMILY_NXP_IMXRT
config SOC_SERIES
default "imxrt11xx" if SOC_SERIES_IMXRT11XX
config SOC_MIMXRT1166
bool
select SOC_SERIES_IMXRT11XX
config SOC_MIMXRT1176
bool
select SOC_SERIES_IMXRT11XX
config SOC_MIMXRT1166_CM4
bool
select SOC_MIMXRT1166
config SOC_MIMXRT1166_CM7
bool
select SOC_MIMXRT1166
config SOC_MIMXRT1176_CM4
bool
select SOC_MIMXRT1176
config SOC_MIMXRT1176_CM7
bool
select SOC_MIMXRT1176
config SOC
default "mimxrt1166" if SOC_MIMXRT1166
default "mimxrt1176" if SOC_MIMXRT1176
config SOC_PART_NUMBER_MIMXRT1166DVM6A
bool
config SOC_PART_NUMBER_MIMXRT1176AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1176CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1176DVMAA
bool
config SOC_PART_NUMBER_MIMXRT1175AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1175CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1175DVMAA
bool
config SOC_PART_NUMBER_MIMXRT1173CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1172AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1172CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1172DVMAA
bool
config SOC_PART_NUMBER_MIMXRT1171AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1171CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1171DVMAA
bool
config SOC_PART_NUMBER
default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A
default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A
default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA
default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A
default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A
default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A
default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA
default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A
default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A
default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A
default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA
default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A
default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A
default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA

65
soc/nxp/imxrt/imxrt11xx/flexspi.c Normal file
View File

@@ -0,0 +1,65 @@
/*
* Copyright (c) 2023, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <fsl_clock.h>
#include <fsl_flexspi.h>
#include <soc.h>
#include <errno.h>
#include <zephyr/irq.h>
#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate)
{
clock_name_t root;
uint32_t root_rate;
FLEXSPI_Type *flexspi;
clock_root_t flexspi_clk;
clock_ip_name_t clk_gate;
uint32_t divider;
switch (clock_name) {
case IMX_CCM_FLEXSPI_CLK:
flexspi_clk = kCLOCK_Root_Flexspi1;
flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi));
clk_gate = kCLOCK_Flexspi1;
break;
case IMX_CCM_FLEXSPI2_CLK:
flexspi_clk = kCLOCK_Root_Flexspi2;
flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi2));
clk_gate = kCLOCK_Flexspi2;
break;
default:
return -ENOTSUP;
}
root = CLOCK_GetRootClockSource(flexspi_clk,
CLOCK_GetRootClockMux(flexspi_clk));
/* Get clock root frequency */
root_rate = CLOCK_GetFreq(root);
/* Select a divider based on root clock frequency. We round the
* divider up, so that the resulting clock frequency is lower than
* requested when we can't output the exact requested frequency
*/
divider = ((root_rate + (rate - 1)) / rate);
/* Cap divider to max value */
divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK);
while (FLEXSPI_GetBusIdleStatus(flexspi) == false) {
/* Spin */
}
FLEXSPI_Enable(flexspi, false);
CLOCK_DisableClock(clk_gate);
CLOCK_SetRootClockDiv(flexspi_clk, divider);
CLOCK_EnableClock(clk_gate);
FLEXSPI_Enable(flexspi, true);
FLEXSPI_SoftwareReset(flexspi);
return 0;
}

21
soc/nxp/imxrt/imxrt11xx/linker.ld Normal file
View File

@@ -0,0 +1,21 @@
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
MEMORY
{
#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0))
#endif
}
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>

0
soc/soc_legacy/arm/nxp_imx/rt/pinctrl_rt11xx.h → soc/nxp/imxrt/imxrt11xx/pinctrl_soc.h
View File

0
soc/soc_legacy/arm/nxp_imx/rt/power_rt11xx.c → soc/nxp/imxrt/imxrt11xx/power.c
View File

0
soc/soc_legacy/arm/nxp_imx/rt/power_rt11xx.h → soc/nxp/imxrt/imxrt11xx/power.h
View File

6
soc/soc_legacy/arm/nxp_imx/rt/soc_rt11xx.c → soc/nxp/imxrt/imxrt11xx/soc.c
View File

@@ -15,7 +15,7 @@
#include <fsl_gpc.h>
#include <fsl_pmu.h>
#include <fsl_dcdc.h>
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
#include <fsl_flexspi_nor_boot.h>
#endif
#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
@@ -120,7 +120,7 @@ static const clock_video_pll_config_t videoPllConfig = {
};
#endif
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
const __imx_boot_data_section BOOT_DATA_T boot_data = {
#ifdef CONFIG_XIP
.start = CONFIG_FLASH_BASE_ADDRESS,
@@ -523,7 +523,7 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#endif
#if !(defined(CONFIG_CODE_FLEXSPI) || defined(CONFIG_CODE_FLEXSPI2)) && \
#if !(DT_NODE_HAS_COMPAT(DT_CHOSEN(flash), nxp_imx_flexspi)) && \
defined(CONFIG_MEMC_MCUX_FLEXSPI) && \
DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay)
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */

48
soc/nxp/imxrt/imxrt11xx/soc.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <fsl_common.h>
/* Add include for DTS generated information */
#include <zephyr/devicetree.h>
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_I2S_MCUX_SAI
void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src,
uint32_t clk_pre_div, uint32_t clk_src_div);
#endif
#if CONFIG_MIPI_DSI
void imxrt_pre_init_display_interface(void);
void imxrt_post_init_display_interface(void);
#endif
void flexspi_clock_set_div(uint32_t value);
uint32_t flexspi_clock_get_freq(void);
#ifdef CONFIG_MEMC
uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate);
#endif
#ifdef __cplusplus
}
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */

20
soc/soc_legacy/arm/nxp_imx/rt6xx/CMakeLists.txt → soc/nxp/imxrt/imxrt6xx/CMakeLists.txt
View File

@@ -4,17 +4,13 @@
# SPDX-License-Identifier: Apache-2.0
#
zephyr_sources(
soc.c
)
zephyr_include_directories(.)
zephyr_sources_ifdef(CONFIG_PM
power.c
)
zephyr_sources(soc.c)
zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP
flash_clock_setup.c
)
zephyr_sources_ifdef(CONFIG_PM power.c)
zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP flash_clock_setup.c)
zephyr_library_include_directories(
${ZEPHYR_BASE}/kernel/include
@@ -23,12 +19,6 @@ zephyr_library_include_directories(
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER
ROM_START SORT_KEY 0 boot_header.ld)
zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
SECTIONS usb.ld)
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM)
endif()

65
soc/nxp/imxrt/imxrt6xx/Kconfig Normal file
View File

@@ -0,0 +1,65 @@
# Copyright 2020, 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMXRT6XX
select ARM
select CPU_CORTEX_M33
select CPU_CORTEX_M_HAS_DWT
select CLOCK_CONTROL
select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP
select PLATFORM_SPECIFIC_INIT
select HAS_PM
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select ARMV8_M_DSP
select ARM_TRUSTZONE_M
select CPU_CORTEX_M_HAS_SYSTICK
select HAS_MCUX
select HAS_MCUX_SYSCON
select HAS_MCUX_FLEXCOMM
select HAS_MCUX_FLEXSPI
select HAS_MCUX_CACHE
select HAS_MCUX_LPC_DMA
select HAS_MCUX_LPADC
select HAS_MCUX_OS_TIMER
select HAS_MCUX_LPC_RTC
select HAS_MCUX_TRNG
select HAS_MCUX_SCTIMER
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select INIT_SYS_PLL
select HAS_MCUX_USB_LPCIP3511
select HAS_MCUX_CTIMER
if SOC_SERIES_IMXRT6XX
config MCUX_CORE_SUFFIX
default "_cm33" if SOC_MIMXRT685S_CM33
config INIT_SYS_PLL
bool "Initialize SYS PLL"
config INIT_AUDIO_PLL
bool "Initialize Audio PLL"
config XTAL_SYS_CLK_HZ
int "External oscillator frequency"
help
Set the external oscillator frequency in Hz. This should be set by the
board's defconfig.
config SYSOSC_SETTLING_US
int "System oscillator settling time"
help
Set the board system oscillator settling time in us. This should be set by the
board's defconfig.
config IMXRT6XX_CODE_CACHE
bool "Code cache"
default y
help
Enable code cache for FlexSPI region at boot. If this Kconfig is
cleared, the CACHE64 controller will be disabled during SOC init
endif

44
soc/soc_legacy/arm/nxp_imx/rt6xx/Kconfig.defconfig.series → soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig
View File

@@ -1,15 +1,22 @@
# i.MX RT6XX series configuration options
# Copyright (c) 2020, NXP
# Copyright 2020, 2024 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX_RT6XX
if SOC_SERIES_IMXRT6XX
config SOC_SERIES
default "rt6xx"
# alias for hal
config SOC_SERIES_IMX_RT6XX
bool
default y
# another alias for hal
config SOC_SERIES_IMXRT_6XX
bool
default y
config ROM_START_OFFSET
default 0x1200 if NXP_IMX_RT6XX_BOOT_HEADER
default 0x1200 if NXP_IMXRT_BOOT_HEADER
config NUM_IRQS
default 60
@@ -17,6 +24,12 @@ config NUM_IRQS
config ZTEST_NO_YIELD
default y if (ZTEST && PM)
# Setup LMA adjustment if using the RAMLOADER feature of ROM
FLASH_CHOSEN := zephyr,flash
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1)
config BUILD_OUTPUT_ADJUST_LMA
default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER
# The base address is determined from the zephyr,flash node with the following
# precedence:
@@ -76,6 +89,25 @@ config TEST_EXTRA_STACK_SIZE
default 1024
endif # MBEDTLS
source "soc/soc_legacy/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt6*"
config I2S_MCUX_FLEXCOMM
select INIT_AUDIO_PLL
if MCUX_OS_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
endif # MCUX_OS_TIMER
if CORTEX_M_SYSTICK
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 250105263
endif # CORTEX_M_SYSTICK
choice USB_MCUX_CONTROLLER_TYPE
default USB_DC_NXP_LPCIP3511
endchoice
endif # SOC_SERIES_MIMXRT6XX

33
soc/nxp/imxrt/imxrt6xx/Kconfig.soc Normal file
View File

@@ -0,0 +1,33 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMXRT6XX
bool
select SOC_FAMILY_NXP_IMXRT
config SOC_SERIES
default "imxrt6xx" if SOC_SERIES_IMXRT6XX
config SOC_MIMXRT685S_CM33
bool
select SOC_SERIES_IMXRT6XX
config SOC
default "mimxrt685s" if SOC_MIMXRT685S_CM33
config SOC_PART_NUMBER_MIMXRT685SFVKB
bool
select SOC_MIMXRT685S_CM33
config SOC_PART_NUMBER_MIMXRT685SFFOB
bool
select SOC_MIMXRT685S_CM33
config SOC_PART_NUMBER_MIMXRT685SFAWBR
bool
select SOC_MIMXRT685S_CM33
config SOC_PART_NUMBER
default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB
default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB
default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR

0
soc/soc_legacy/arm/nxp_imx/rt6xx/flash_clock_setup.c → soc/nxp/imxrt/imxrt6xx/flash_clock_setup.c
View File

0
soc/soc_legacy/arm/nxp_imx/rt6xx/flash_clock_setup.h → soc/nxp/imxrt/imxrt6xx/flash_clock_setup.h
View File

0
soc/soc_legacy/arm/nxp_imx/rt6xx/pinctrl_soc.h → soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h
View File

0
soc/soc_legacy/arm/nxp_imx/rt6xx/power.c → soc/nxp/imxrt/imxrt6xx/power.c
View File

8
soc/soc_legacy/arm/nxp_imx/rt6xx/soc.c → soc/nxp/imxrt/imxrt6xx/soc.c
View File

@@ -80,7 +80,7 @@ extern uint32_t SystemCoreClock;
/* Main stack pointer */
extern char z_main_stack[];
#ifdef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
extern char _flash_used[];
extern void z_arm_reset(void);
extern void z_arm_nmi(void);
@@ -122,7 +122,7 @@ __imx_boot_ivt_section void (* const image_vector_table[])(void) = {
z_arm_exc_spurious,
#endif
};
#endif /* CONFIG_NXP_IMX_RT6XX_BOOT_HEADER */
#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */
#if CONFIG_USB_DC_NXP_LPCIP3511
@@ -371,7 +371,7 @@ static int nxp_rt600_init(void)
void z_arm_platform_init(void)
{
#ifndef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER
#ifndef CONFIG_NXP_IMXRT_BOOT_HEADER
/*
* If boot did not proceed using a boot header, we should not assume
* the core is in reset state. Disable the MPU and correctly
@@ -385,7 +385,7 @@ void z_arm_platform_init(void)
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
/* Set stack pointer */
__set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE));
#endif /* !CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */
#endif /* !CONFIG_NXP_IMXRT_BOOT_HEADER */
/* This is provided by the SDK */
SystemInit();
}

0
soc/soc_legacy/arm/nxp_imx/rt6xx/soc.h → soc/nxp/imxrt/imxrt6xx/soc.h
View File

0
soc/soc_legacy/arm/nxp_imx/rt/mpu_regions.c → soc/nxp/imxrt/mpu_regions.c
View File

28
soc/nxp/imxrt/soc.yml Normal file
View File

@@ -0,0 +1,28 @@
family:
- name: nxp_imxrt
series:
- name: imxrt10xx
socs:
- name: mimxrt1011
- name: mimxrt1015
- name: mimxrt1021
- name: mimxrt1024
- name: mimxrt1042
- name: mimxrt1051
- name: mimxrt1052
- name: mimxrt1061
- name: mimxrt1062
- name: mimxrt1064
- name: imxrt11xx
socs:
- name: mimxrt1166
cpuclusters:
- name: cm7
- name: cm4
- name: mimxrt1176
cpuclusters:
- name: cm7
- name: cm4
- name: imxrt6xx
socs:
- name: mimxrt685s

2
soc/soc_legacy/arm/nxp_imx/rt6xx/usb.ld → soc/nxp/imxrt/usb.ld
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 NXP
* Copyright 2021-2022, 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/

76
soc/soc_legacy/arm/nxp_imx/rt/CMakeLists.txt
View File

@@ -1,76 +0,0 @@
#
# Copyright (c) 2017-2021, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX soc_rt11xx.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT10XX soc_rt10xx.c)
zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER
ROM_START SORT_KEY 0 boot_header.ld)
# Add custom mpu regions
zephyr_sources(mpu_regions.c)
zephyr_linker_section_configure(
SECTION .rom_start
INPUT ".boot_hdr.conf"
OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET}
KEEP
PRIO 10
)
if(CONFIG_DEVICE_CONFIGURATION_DATA)
set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data")
endif()
if(CONFIG_PM)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX power_rt11xx.c)
endif()
if (CONFIG_SOC_SERIES_IMX_RT10XX AND CONFIG_MEMC_MCUX_FLEXSPI)
zephyr_sources(flexspi_rt10xx.c)
if (CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flexspi_rt10xx.c LOCATION ITCM_TEXT)
endif()
endif ()
if (CONFIG_SOC_SERIES_IMX_RT11XX AND CONFIG_MEMC_MCUX_FLEXSPI)
zephyr_sources(flexspi_rt11xx.c)
if (CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flexspi_rt11xx.c LOCATION ITCM_TEXT)
endif()
endif ()
if (CONFIG_PM AND CONFIG_SOC_SERIES_IMX_RT10XX)
zephyr_sources(power_rt10xx.c)
zephyr_code_relocate(FILES power_rt10xx.c LOCATION ITCM_TEXT)
if (CONFIG_SOC_MIMXRT1064)
zephyr_sources(lpm_rt1064.c)
zephyr_code_relocate(FILES lpm_rt1064.c LOCATION ITCM_TEXT)
endif()
endif()
zephyr_compile_definitions(
XIP_EXTERNAL_FLASH
)
zephyr_compile_definitions_ifdef(CONFIG_ENTROPY_MCUX_CAAM CACHE_MODE_WRITE_THROUGH)
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER DATA_SECTION_IS_CACHEABLE=1)
# flexram header
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc)
zephyr_linker_section_configure(
SECTION .rom_start
INPUT ".boot_hdr.ivt"
".boot_hdr.data"
${boot_hdr_dcd_data_section}
OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET}
KEEP
PRIO 11
)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

24
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010
View File

@@ -1,24 +0,0 @@
# i.MX RT1010
# Copyright (c) 2019, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1011
config SOC
string
default "mimxrt1011"
config NUM_IRQS
default 80
config DCDC_VALUE
default 0x12
config GPIO
default y
config FLEXSPI_CONFIG_BLOCK_OFFSET
default 0x400
endif # SOC_MIMXRT1010

20
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015
View File

@@ -1,20 +0,0 @@
# i.MX RT1015
# Copyright (c) 2019, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1015
config SOC
default "mimxrt1015"
config NUM_IRQS
default 142
config DCDC_VALUE
default 0x12
config GPIO
default y
endif # SOC_MIMXRT1015

20
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021
View File

@@ -1,20 +0,0 @@
# i.MX RT1021
# Copyright (c) 2018, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1021
config SOC
default "mimxrt1021"
config NUM_IRQS
default 142
config DCDC_VALUE
default 0x12
config GPIO
default y
endif # SOC_MIMXRT1021

20
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024
View File

@@ -1,20 +0,0 @@
# i.MX RT1024
# Copyright (c) 2020, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1024
config SOC
default "mimxrt1024"
config NUM_IRQS
default 142
config DCDC_VALUE
default 0x12
config GPIO
default y
endif # SOC_MIMXRT1024

19
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1042
View File

@@ -1,19 +0,0 @@
# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1042
config SOC
default "mimxrt1042"
config NUM_IRQS
default 157
config GPIO
default y
# Set DCDC to 1.275V for 600 MHz AHB operation
config DCDC_VALUE
default 0x13
endif # SOC_MIMXRT1042

17
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052
View File

@@ -1,17 +0,0 @@
# i.MX RT1052
# Copyright (c) 2017, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1052
config SOC
default "mimxrt1052"
config NUM_IRQS
default 160
config GPIO
default y
endif # SOC_MIMXRT1052

17
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062
View File

@@ -1,17 +0,0 @@
# i.MX RT1062
# Copyright (c) 2018, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1062
config SOC
default "mimxrt1062"
config NUM_IRQS
default 160
config GPIO
default y
endif # SOC_MIMXRT1062

17
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064
View File

@@ -1,17 +0,0 @@
# i.MX RT1064
# Copyright (c) 2018, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1064
config SOC
default "mimxrt1064"
config NUM_IRQS
default 160
config GPIO
default y
endif # SOC_MIMXRT1064

20
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4
View File

@@ -1,20 +0,0 @@
# i.MX RT1160 CM4
# Copyright (c) 2021, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1166_CM4
config SOC
default "mimxrt1166_cm4"
config NUM_IRQS
default 218
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 240000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1166_CM4

20
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7
View File

@@ -1,20 +0,0 @@
# i.MX RT1160 CM7
# Copyright (c) 2021, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1166_CM7
config SOC
default "mimxrt1166_cm7"
config NUM_IRQS
default 218
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 600000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1166_CM7

20
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4
View File

@@ -1,20 +0,0 @@
# i.MX RT1170 CM4
# Copyright (c) 2021, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1176_CM4
config SOC
default "mimxrt1176_cm4"
config NUM_IRQS
default 218
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1170_CM4

20
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7
View File

@@ -1,20 +0,0 @@
# i.MX RT1170 CM7
# Copyright (c) 2021, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT1176_CM7
config SOC
default "mimxrt1176_cm7"
config NUM_IRQS
default 218
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 996000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1176_CM7

14
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.series
View File

@@ -1,14 +0,0 @@
# iMX RT series
# Copyright (c) 2017-2021,2023 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMX_RT
bool "i.MX RT Series"
select ARM
select SOC_FAMILY_IMX
select CLOCK_CONTROL
select HAS_PM
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
help
Enable support for i.MX RT MCU series

837
soc/soc_legacy/arm/nxp_imx/rt/Kconfig.soc
View File

@@ -1,837 +0,0 @@
# i.MX RT series
# Copyright 2017-2021,2023 NXP
# SPDX-License-Identifier: Apache-2.0
choice
prompt "i.MX RT Selection"
depends on SOC_SERIES_IMX_RT
config SOC_MIMXRT1011
bool "SOC_MIMXRT1011"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_TRNG
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select INIT_ENET_PLL
select HAS_MCUX_USB_EHCI
select HAS_MCUX_EDMA
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1015
bool "SOC_MIMXRT1015"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_TRNG
select CPU_HAS_FPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ENET_PLL
select HAS_MCUX_USB_EHCI
select HAS_MCUX_EDMA
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1021
bool "SOC_MIMXRT1021"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_ENET
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_SEMC
select HAS_MCUX_TRNG
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ENET_PLL
select HAS_MCUX_USB_EHCI
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_EDMA
select HAS_MCUX_FLEXCAN
select HAS_MCUX_PWM
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1024
bool "SOC_MIMXRT1024"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_ENET
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_SEMC
select HAS_MCUX_TRNG
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ENET_PLL
select HAS_MCUX_USB_EHCI
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_EDMA
select HAS_MCUX_FLEXCAN
select HAS_MCUX_SRC
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1042
bool "SOC_MIMXRT1042"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_FLEXSPI
select HAS_MCUX_SEMC
select HAS_MCUX_IGPIO
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select HAS_MCUX_EDMA
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1051
bool "SOC_MIMXRT1051"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_ENET
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_SEMC
select HAS_MCUX_TRNG
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select HAS_MCUX_USB_EHCI
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_EDMA
select HAS_MCUX_FLEXCAN
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1052
bool "SOC_MIMXRT1052"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_SEMC
select HAS_MCUX_TRNG
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select HAS_MCUX_USB_EHCI
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_EDMA
select HAS_MCUX_FLEXCAN
select HAS_MCUX_PWM
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_MCUX_SRC
select HAS_SWO
select HAS_MCUX_XBARA
config SOC_MIMXRT1061
bool "SOC_MIMXRT1061"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_ENET
select HAS_MCUX_FLEXSPI
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_SEMC
select HAS_MCUX_TRNG
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select HAS_MCUX_USB_EHCI
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_EDMA
select HAS_MCUX_FLEXCAN
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1062
bool "SOC_MIMXRT1062"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
select HAS_MCUX_FLEXSPI
select HAS_MCUX_PWM
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_QTMR
select HAS_MCUX_SEMC
select HAS_MCUX_SNVS
select HAS_MCUX_TRNG
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select HAS_MCUX_USB_EHCI
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_EDMA
select HAS_MCUX_FLEXCAN
select HAS_MCUX_I2S
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_MCUX_ADC_ETC
select HAS_MCUX_SRC
select HAS_SWO
select HAS_MCUX_XBARA
config SOC_MIMXRT1064
bool "SOC_MIMXRT1064"
select SOC_SERIES_IMX_RT10XX
select HAS_MCUX
select HAS_MCUX_CACHE
select HAS_MCUX_12B1MSPS_SAR
select HAS_MCUX_CCM
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
select HAS_MCUX_FLEXSPI
select HAS_MCUX_PWM
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select HAS_MCUX_QTMR
select HAS_MCUX_SEMC
select HAS_MCUX_SNVS
select HAS_MCUX_SRC
select HAS_MCUX_TRNG
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select HAS_MCUX_USB_EHCI
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_CSI
select HAS_MCUX_EDMA
select HAS_MCUX_FLEXCAN
select HAS_MCUX_GPC
select HAS_MCUX_DCDC
select HAS_MCUX_PMU
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1176_CM7
bool "SOC_MIMXRT1176_CM7"
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select SOC_SERIES_IMX_RT11XX
select HAS_MCUX_CACHE
select HAS_MCUX
select HAS_MCUX_SEMC
select HAS_MCUX_CCM_REV2
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPADC
select HAS_MCUX_LPUART
select HAS_MCUX_ELCDIF
select HAS_MCUX_MIPI_DSI
select HAS_MCUX_GPT
select HAS_MCUX_FLEXSPI
select HAS_MCUX_FLEXCAN
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select INIT_VIDEO_PLL
select HAS_MCUX_EDMA
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select CPU_HAS_FPU_DOUBLE_PRECISION
select BYPASS_LDO_LPSR
select ADJUST_LDO
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
select HAS_MCUX_GPC
select HAS_MCUX_I2S
select HAS_MCUX_USB_EHCI
select HAS_MCUX_ACMP
select HAS_MCUX_SRC_V2
select HAS_MCUX_IOMUXC
select HAS_MCUX_XBARA
select HAS_SWO
config SOC_MIMXRT1176_CM4
bool "SOC_MIMXRT1176_CM4"
select CPU_CORTEX_M4
select SOC_SERIES_IMX_RT11XX
select HAS_MCUX_CACHE
select HAS_MCUX
select HAS_MCUX_SEMC
select HAS_MCUX_CCM_REV2
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_FLEXSPI
select HAS_MCUX_LPUART
select HAS_MCUX_GPT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select INIT_ARM_PLL
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select INIT_VIDEO_PLL
select HAS_MCUX_EDMA
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
select HAS_MCUX_GPC
select HAS_MCUX_I2S
select HAS_MCUX_ACMP
select HAS_MCUX_SRC_V2
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1166_CM7
bool "SOC_MIMXRT1166_CM7"
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select SOC_SERIES_IMX_RT11XX
select HAS_MCUX_CACHE
select HAS_MCUX
select HAS_MCUX_SEMC
select HAS_MCUX_CCM_REV2
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPADC
select HAS_MCUX_LPUART
select HAS_MCUX_FLEXSPI
select HAS_MCUX_GPT
select HAS_MCUX_FLEXCAN
select CPU_HAS_ARM_MPU
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select INIT_ARM_PLL
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select INIT_VIDEO_PLL
select HAS_MCUX_EDMA
select CPU_HAS_FPU_DOUBLE_PRECISION
select BYPASS_LDO_LPSR
select ADJUST_LDO
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
select HAS_MCUX_GPC
select HAS_MCUX_USB_EHCI
select HAS_MCUX_SRC_V2
select HAS_MCUX_IOMUXC
select HAS_SWO
config SOC_MIMXRT1166_CM4
bool "SOC_MIMXRT1166_CM4"
select CPU_CORTEX_M4
select SOC_SERIES_IMX_RT11XX
select HAS_MCUX_CACHE
select HAS_MCUX
select HAS_MCUX_SEMC
select HAS_MCUX_CCM_REV2
select HAS_MCUX_IGPIO
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_LPUART
select HAS_MCUX_FLEXSPI
select HAS_MCUX_GPT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select INIT_ARM_PLL
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
select INIT_VIDEO_PLL
select HAS_MCUX_EDMA
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
select HAS_MCUX_GPC
select HAS_MCUX_SRC_V2
select HAS_MCUX_IOMUXC
select HAS_SWO
endchoice
if SOC_SERIES_IMX_RT
config SOC_PART_NUMBER_MIMXRT1011CAE4A
bool
config SOC_PART_NUMBER_MIMXRT1011DAE5A
bool
config SOC_PART_NUMBER_MIMXRT1015CAF4A
bool
config SOC_PART_NUMBER_MIMXRT1015DAF5A
bool
config SOC_PART_NUMBER_MIMXRT1021CAF4A
bool
config SOC_PART_NUMBER_MIMXRT1021CAG4A
bool
config SOC_PART_NUMBER_MIMXRT1021DAF5A
bool
config SOC_PART_NUMBER_MIMXRT1021DAG5A
bool
config SOC_PART_NUMBER_MIMXRT1024CAG4A
bool
config SOC_PART_NUMBER_MIMXRT1024DAG5A
bool
config SOC_PART_NUMBER_MIMXRT1041DFP6B
bool
config SOC_PART_NUMBER_MIMXRT1041DJM6B
bool
config SOC_PART_NUMBER_MIMXRT1041XFP5B
bool
config SOC_PART_NUMBER_MIMXRT1041XJM5B
bool
config SOC_PART_NUMBER_MIMXRT1042DFP6B
bool
config SOC_PART_NUMBER_MIMXRT1042DJM6B
bool
config SOC_PART_NUMBER_MIMXRT1042XFP5B
bool
config SOC_PART_NUMBER_MIMXRT1042XJM5B
bool
config SOC_PART_NUMBER_MIMXRT1051CVL5A
bool
config SOC_PART_NUMBER_MIMXRT1051DVL6A
bool
config SOC_PART_NUMBER_MIMXRT1052CVJ5B
bool
config SOC_PART_NUMBER_MIMXRT1052CVL5A
bool
config SOC_PART_NUMBER_MIMXRT1052CVL5B
bool
config SOC_PART_NUMBER_MIMXRT1052DVJ6B
bool
config SOC_PART_NUMBER_MIMXRT1052DVL6A
bool
config SOC_PART_NUMBER_MIMXRT1052DVL6B
bool
config SOC_PART_NUMBER_MIMXRT1061CVL5A
bool
config SOC_PART_NUMBER_MIMXRT1061DVL6A
bool
config SOC_PART_NUMBER_MIMXRT1062CVJ5A
bool
config SOC_PART_NUMBER_MIMXRT1062CVJ5B
bool
config SOC_PART_NUMBER_MIMXRT1062CVL5A
bool
config SOC_PART_NUMBER_MIMXRT1062DVJ6A
bool
config SOC_PART_NUMBER_MIMXRT1062DVL6A
bool
config SOC_PART_NUMBER_MIMXRT1064CVL5A
bool
config SOC_PART_NUMBER_MIMXRT1064DVL6A
bool
config SOC_PART_NUMBER_MIMXRT1166DVM6A
bool
config SOC_PART_NUMBER_MIMXRT1176AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1176CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1176DVMAA
bool
config SOC_PART_NUMBER_MIMXRT1175AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1175CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1175DVMAA
bool
config SOC_PART_NUMBER_MIMXRT1173CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1172AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1172CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1172DVMAA
bool
config SOC_PART_NUMBER_MIMXRT1171AVM8A
bool
config SOC_PART_NUMBER_MIMXRT1171CVM8A
bool
config SOC_PART_NUMBER_MIMXRT1171DVMAA
bool
config SOC_PART_NUMBER_IMX_RT
string
default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A
default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A
default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A
default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A
default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A
default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A
default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A
default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A
default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A
default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B
default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B
default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B
default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B
default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B
default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B
default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B
default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B
default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A
default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B
default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A
default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B
default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A
default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A
default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A
default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B
default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A
default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A
default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A
default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A
default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A
default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A
default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A
default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA
default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A
default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A
default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A
default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA
default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A
default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A
default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A
default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA
default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A
default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A
default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA
help
This string holds the full part number of the SoC. It is a hidden option
that you should not set directly. The part number selection choice defines
the default value for this string.
config SOC_SERIES_IMX_RT10XX
bool "i.MX RT 10XX Series"
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select PLATFORM_SPECIFIC_INIT
config SOC_SERIES_IMX_RT11XX
bool "i.MX RT 11XX Series"
select PLATFORM_SPECIFIC_INIT
config INIT_ARM_PLL
bool "Initialize ARM PLL"
config INIT_VIDEO_PLL
bool "Initialize Video PLL"
config INIT_ENET_PLL
bool
help
If y, the Ethernet PLL is initialized. Always enabled on e.g.
MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
for MIMXRT1021").
config DCDC_VALUE
hex "DCDC value for VDD_SOC"
default 0x13
config ADJUST_DCDC
bool "Adjust internal DCDC output"
default y if SOC_SERIES_IMX_RT11XX
config BYPASS_LDO_LPSR
bool "Bypass LDO lpsr"
config ADJUST_LDO
bool "Adjust LDO setting"
config PM_MCUX_GPC
bool "MCUX general power controller driver"
config PM_MCUX_DCDC
bool "MCUX dcdc converter module driver"
config PM_MCUX_PMU
bool "MCUX power management unit driver"
menuconfig NXP_IMX_RT_BOOT_HEADER
bool "Boot header"
depends on (!BOOTLOADER_MCUBOOT) && CPU_CORTEX_M7
help
Enable data structures required by the boot ROM to boot the
application from an external flash device.
if NXP_IMX_RT_BOOT_HEADER
choice BOOT_DEVICE
prompt "Boot device selection"
default BOOT_FLEXSPI_NOR
config BOOT_FLEXSPI_NOR
bool "FlexSPI serial NOR"
config BOOT_FLEXSPI_NAND
bool "FlexSPI serial NAND"
config BOOT_SEMC_NOR
bool "SEMC parallel NOR"
config BOOT_SEMC_NAND
bool "SEMC parallel NAND"
endchoice
config FLEXSPI_CONFIG_BLOCK_OFFSET
hex "FlexSPI config block offset"
default 0x0 if BOOT_FLEXSPI_NOR
help
FlexSPI configuration block consists of parameters regarding specific
flash devices including read command sequence, quad mode enablement
sequence (optional), etc. The boot ROM expects FlexSPI configuration
parameter to be presented in serial nor flash.
config IMAGE_VECTOR_TABLE_OFFSET
hex "Image vector table offset"
default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
help
The Image Vector Table (IVT) provides the boot ROM with pointers to
the application entry point and device configuration data. The boot
ROM requires a fixed IVT offset for each type of boot device.
config DEVICE_CONFIGURATION_DATA
bool "Device configuration data"
help
Device configuration data (DCD) provides a sequence of commands to
the boot ROM to initialize components such as an SDRAM. This is
useful if your application expects components like SDRAM to be
initialized at boot time.
endif # NXP_IMX_RT_BOOT_HEADER
choice CODE_LOCATION
prompt "Code location selection"
default CODE_ITCM
config CODE_SEMC
bool "Link code into external SEMC-controlled memory"
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
config CODE_ITCM
bool "Link code into internal instruction tightly coupled memory (ITCM)"
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
config CODE_FLEXSPI
bool "Link code into external FlexSPI-controlled memory"
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
config CODE_FLEXSPI2
bool "Link code into internal FlexSPI-controlled memory"
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
config CODE_SRAM0
bool "Link code into RAM_L memory (RAM_L)"
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
config CODE_OCRAM
bool "Link code into OCRAM memory (OCRAM-M4)"
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
endchoice
config NXP_IMX_EXTERNAL_SDRAM
bool "Allow access to external SDRAM region"
help
Enable access to external SDRAM region managed by the SEMC. This
setting should be enabled when the application uses SDRAM, or
an MPU region will be defined to disable cached access to the
SDRAM memory space.
config NXP_IMX_RT_ROM_RAMLOADER
depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMX_RT_BOOT_HEADER
# Required so that debugger will load image to correct offset
select BUILD_OUTPUT_HEX
bool "Create output image that IMX RT ROM can load from FlexSPI to ram"
help
Builds an output image that the IMX RT BootROM can load from the
FlexSPI boot device into RAM region. The image will be loaded
from FLEXSPI into the region specified by `zephyr,flash` node.
# Setup LMA adjustment if using the RAMLOADER feature of ROM
FLASH_CHOSEN := zephyr,flash
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1)
config BUILD_OUTPUT_ADJUST_LMA
default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER
config SECOND_CORE_MCUX
bool "Dual core operation on the RT11xx series"
depends on SOC_SERIES_IMX_RT11XX
help
Indicates the second core will be enabled, and the part will run
in dual core mode. Enables dual core operation on the RT11xx series,
by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU.
The M4 image will be loaded from flash into RAM based off a
generated header specifying the VMA and LMA of each memory section
to load
endif # SOC_SERIES_IMX_RT

15
soc/soc_legacy/arm/nxp_imx/rt/boot_header.ld
View File

@@ -1,15 +0,0 @@
/*
* Copyright (c) 2019 NXP
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
KEEP(*(.boot_hdr.conf))
. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.data))
#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
KEEP(*(.boot_hdr.dcd_data))
#endif

15
soc/soc_legacy/arm/nxp_imx/rt/pinctrl_soc.h
View File

@@ -1,15 +0,0 @@
/*
* Copyright (c) 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX)
#include "pinctrl_rt10xx.h"
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#include "pinctrl_rt11xx.h"
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ */

32
soc/soc_legacy/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33
View File

@@ -1,32 +0,0 @@
# NXP MIMXRT6XX platform configuration options
# Copyright (c) 2020, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMXRT685S_CM33
config SOC
default "mimxrt685s_cm33"
config I2S_MCUX_FLEXCOMM
select INIT_AUDIO_PLL
if MCUX_OS_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
endif # MCUX_OS_TIMER
if CORTEX_M_SYSTICK
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 250105263
endif # CORTEX_M_SYSTICK
choice USB_MCUX_CONTROLLER_TYPE
default USB_DC_NXP_LPCIP3511
endchoice
endif # SOC_MIMXRT685S_CM33

17
soc/soc_legacy/arm/nxp_imx/rt6xx/Kconfig.series
View File

@@ -1,17 +0,0 @@
# i.MX RT6XX Series
# Copyright (c) 2020, NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMX_RT6XX
bool "i.MX RT6XX Series Family MCU"
select ARM
select CPU_CORTEX_M33
select CPU_CORTEX_M_HAS_DWT
select SOC_FAMILY_IMX
select CLOCK_CONTROL
select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP
select PLATFORM_SPECIFIC_INIT
select HAS_PM
help
Enable support for i.MX RT6XX Series MCU series

136
soc/soc_legacy/arm/nxp_imx/rt6xx/Kconfig.soc
View File

@@ -1,136 +0,0 @@
# i.MX RT6XX Series
# Copyright (c) 2020, NXP
# SPDX-License-Identifier: Apache-2.0
choice
prompt "i.MX RT6XX Series MCU Selection"
depends on SOC_SERIES_IMX_RT6XX
config SOC_MIMXRT685S_CM33
bool "SOC_MIMXRT685S M33"
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select ARMV8_M_DSP
select ARM_TRUSTZONE_M
select CPU_CORTEX_M_HAS_SYSTICK
select HAS_MCUX
select HAS_MCUX_SYSCON
select HAS_MCUX_FLEXCOMM
select HAS_MCUX_FLEXSPI
select HAS_MCUX_CACHE
select HAS_MCUX_LPC_DMA
select HAS_MCUX_LPADC
select HAS_MCUX_OS_TIMER
select HAS_MCUX_LPC_RTC
select HAS_MCUX_TRNG
select HAS_MCUX_SCTIMER
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select INIT_SYS_PLL
select HAS_MCUX_USB_LPCIP3511
select HAS_MCUX_CTIMER
endchoice
if SOC_SERIES_IMX_RT6XX
config SOC_PART_NUMBER_MIMXRT685SFVKB
bool
config SOC_PART_NUMBER_MIMXRT685SFFOB
bool
config SOC_PART_NUMBER_MIMXRT685SFAWBR
bool
config SOC_PART_NUMBER_IMX_RT6XX
string
default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB
default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB
default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR
help
This string holds the full part number of the SoC. It is a hidden
option that you should not set directly. The part number selection
choice defines the default value for this string.
config INIT_SYS_PLL
bool "Initialize SYS PLL"
config INIT_AUDIO_PLL
bool "Initialize Audio PLL"
config XTAL_SYS_CLK_HZ
int "External oscillator frequency"
help
Set the external oscillator frequency in Hz. This should be set by the
board's defconfig.
config SYSOSC_SETTLING_US
int "System oscillator settling time"
help
Set the board system oscillator settling time in us. This should be set by the
board's defconfig.
menuconfig NXP_IMX_RT6XX_BOOT_HEADER
bool "Boot header"
depends on !BOOTLOADER_MCUBOOT
help
Enable data structures required by the boot ROM to boot the
application from an external flash device.
if NXP_IMX_RT6XX_BOOT_HEADER
choice BOOT_DEVICE
prompt "Boot device selection"
default BOOT_FLEXSPI_NOR
config BOOT_FLEXSPI_NOR
bool "FlexSPI serial NOR"
endchoice
config FLASH_CONFIG_OFFSET
hex "Flash config data offset"
default 0x400
help
The flash config offset provides the boot ROM with the on-board
flash type and parameters. The boot ROM requires a fixed flash config
offset for FlexSPI device.
config IMAGE_VECTOR_TABLE_OFFSET
hex "Image vector table offset"
default 0x1000
help
The Image Vector Table (IVT) provides the boot ROM with pointers to
the application entry point and device configuration data. The boot
ROM requires a fixed IVT offset for each type of boot device.
config NXP_IMX_RT_ROM_RAMLOADER
depends on !FLASH_MCUX_FLEXSPI_XIP
# Required so that debugger will load image to correct offset
select BUILD_OUTPUT_HEX
bool "Create output image that IMX RT ROM can load from FlexSPI to ram"
help
Builds an output image that the IMX RT BootROM can load from the
FlexSPI boot device into RAM region. The image will be loaded
from FLEXSPI into the region specified by `zephyr,flash` node.
# Setup LMA adjustment if using the RAMLOADER feature of ROM
FLASH_CHOSEN := zephyr,flash
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1)
config BUILD_OUTPUT_ADJUST_LMA
default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER
endif # NXP_IMX_RT6XX_BOOT_HEADER
config IMXRT6XX_CODE_CACHE
bool "Code cache"
default y
help
Enable code cache for FlexSPI region at boot. If this Kconfig is
cleared, the CACHE64 controller will be disabled during SOC init
endif # SOC_SERIES_IMX_RT6XX

10
soc/soc_legacy/arm/nxp_imx/rt6xx/boot_header.ld
View File

@@ -1,10 +0,0 @@
/*
* Copyright (c) 2020 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
. = CONFIG_FLASH_CONFIG_OFFSET;
KEEP(*(.flash_conf))
. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
KEEP(*(.boot_hdr.ivt))