boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2

This commit converts the QEMU RISCV-V 64 bit board to Zephyr HWMvW. This
includes the following former targets:
* qemu_riscv64
* qemu_riscv64_smp

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

boards/boards_legacy/riscv/qemu_riscv64/Kconfig.board

@@ -1,24 +0,0 @@
-# Copyright (c) 2019 BayLibre SAS
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_QEMU_RISCV64
-	bool "QEMU RISCV64 target"
-	depends on SOC_RISCV_VIRT
-	select QEMU_TARGET
-	select 64BIT
-	select HAS_COVERAGE_SUPPORT
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-	select RISCV_ISA_RV64I
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI
-
-config BOARD_QEMU_RISCV64_SMP
-	bool "QEMU RISCV64 SMP target"
-	depends on SOC_RISCV_VIRT
-	select QEMU_TARGET
-	select 64BIT
-	select HAS_COVERAGE_SUPPORT
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-	select RISCV_ISA_RV64I
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI

boards/boards_legacy/riscv/qemu_riscv64/Kconfig.defconfig

@@ -1,9 +0,0 @@
-# Copyright (c) 2019 BayLibre SAS
-# SPDX-License-Identifier: Apache-2.0
-
-config BUILD_OUTPUT_BIN
-	default n
-
-config BOARD
-	default "qemu_riscv64" if BOARD_QEMU_RISCV64
-	default "qemu_riscv64_smp" if BOARD_QEMU_RISCV64_SMP

boards/boards_legacy/riscv/qemu_riscv64/qemu_riscv64_smp.dts

@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2022 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <virt.dtsi>
-
-/ {
-	chosen {
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,sram = &ram0;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

boards/boards_legacy/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig

@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_RISCV_VIRT=y
-CONFIG_BOARD_QEMU_RISCV64_SMP=y
-CONFIG_PRIVILEGED_STACK_SIZE=2048
-CONFIG_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_UART_CONSOLE=y
-CONFIG_STACK_SENTINEL=y
-CONFIG_XIP=n
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=2
-CONFIG_QEMU_ICOUNT=n
-
-CONFIG_IDLE_STACK_SIZE=1024
-CONFIG_RISCV_PMP=y
-CONFIG_TICKET_SPINLOCKS=y

boards/qemu/qemu_riscv64/Kconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV64
+	select QEMU_TARGET

boards/qemu/qemu_riscv64/Kconfig.defconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_QEMU_RISCV64
+
+config BUILD_OUTPUT_BIN
+	default n
+
+config HAS_COVERAGE_SUPPORT
+	default y
+
+config QEMU_ICOUNT_SHIFT
+	default 6 if QEMU_ICOUNT
+
+endif # BOARD_QEMU_RISCV64

boards/qemu/qemu_riscv64/Kconfig.qemu_riscv64

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV64
+	select SOC_QEMU_VIRT_RISCV64

boards/qemu/qemu_riscv64/board.yml

@@ -0,0 +1,7 @@
+board:
+  name: qemu_riscv64
+  vendor: qemu
+  socs:
+    - name: qemu_virt_riscv64
+      variants:
+        - name: smp

boards/qemu/qemu_riscv64/qemu_riscv64_defconfig

@@ -1,12 +1,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_RISCV_VIRT=y
-CONFIG_BOARD_QEMU_RISCV64=y
 CONFIG_PRIVILEGED_STACK_SIZE=2048
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
 CONFIG_STACK_SENTINEL=y
-CONFIG_QEMU_ICOUNT_SHIFT=6
 CONFIG_XIP=n
 CONFIG_RISCV_PMP=y

boards/qemu/qemu_riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml

@@ -1,4 +1,4 @@
-identifier: qemu_riscv64_smp
+identifier: qemu_riscv64/qemu_virt_riscv64/smp
 name: QEMU Emulation for RISC-V 64-bit SMP
 type: qemu
 simulation: qemu

boards/qemu/qemu_riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=2
+CONFIG_IDLE_STACK_SIZE=1024
+CONFIG_QEMU_ICOUNT=n

tests/kernel/threads/dynamic_thread_stack/testcase.yaml

@@ -11,7 +11,7 @@ common:
     - qemu_riscv32
     - qemu_riscv32e
     - qemu_riscv64
-    - qemu_riscv64_smp
+    - qemu_riscv64/qemu_virt_riscv64/smp
 
 # Permutations of (pool | alloc | user)
 tests:

tests/posix/pthread_pressure/testcase.yaml

@@ -4,7 +4,7 @@ common:
   arch_exclude:
     - posix
   integration_platforms:
-    - qemu_riscv64_smp
+    - qemu_riscv64/qemu_virt_riscv64/smp
 tests:
   portability.posix.pthread_pressure:
     extra_configs:

tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml

@@ -12,7 +12,7 @@ common:
     - native_sim
     - qemu_cortex_m0
     - qemu_riscv64
-    - qemu_riscv64_smp
+    - qemu_riscv64/qemu_virt_riscv64/smp
     - qemu_malta
     - qemu_arc/qemu_arc_hs6x
     - qemu_leon3

tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml

@@ -33,7 +33,7 @@ tests:
     platform_exclude:
       - qemu_cortex_a9
       - qemu_x86
-      - qemu_riscv64_smp
+      - qemu_riscv64/qemu_virt_riscv64/smp
       - qemu_riscv64
       - qemu_riscv32e
       - qemu_riscv32