boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2

This commit converts the QEMU RISCV-V 32 bit board to Zephyr HWMvW. This
includes the following former targets:
* qemu_riscv32
* qemu_riscv32_smp
* qemu_riscv32_xip

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

boards/boards_legacy/riscv/qemu_riscv32/Kconfig.board

@@ -1,31 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_QEMU_RISCV32
-	bool "QEMU RISCV32 target"
-	depends on SOC_RISCV_VIRT
-	select QEMU_TARGET
-	select HAS_COVERAGE_SUPPORT
-	select CPU_HAS_FPU
-	select RISCV_ISA_RV32I
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI
-
-config BOARD_QEMU_RISCV32_SMP
-	bool "QEMU RISCV32 SMP target"
-	depends on SOC_RISCV_VIRT
-	select QEMU_TARGET
-	select HAS_COVERAGE_SUPPORT
-	select CPU_HAS_FPU
-	select RISCV_ISA_RV32I
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI
-
-config BOARD_QEMU_RISCV32_XIP
-	bool "QEMU RISCV32 XIP target"
-	depends on SOC_SIFIVE_FREEDOM_E340
-	select QEMU_TARGET
-	select HAS_COVERAGE_SUPPORT
-	select CPU_HAS_FPU
-	select RISCV_ISA_RV32I
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI

boards/boards_legacy/riscv/qemu_riscv32/Kconfig.defconfig

@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-config BUILD_OUTPUT_BIN
-	default n
-
-config BOARD
-	default "qemu_riscv32" if BOARD_QEMU_RISCV32
-	default "qemu_riscv32_xip" if BOARD_QEMU_RISCV32_XIP
-	default "qemu_riscv32_smp" if BOARD_QEMU_RISCV32_SMP
-
-# Use thread local storage by default so that
-# this feature gets more CI coverage.
-config THREAD_LOCAL_STORAGE
-	default y

boards/boards_legacy/riscv/qemu_riscv32/board.cmake

@@ -1,23 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-set(SUPPORTED_EMU_PLATFORMS qemu)
-
-set(QEMU_binary_suffix riscv32)
-set(QEMU_CPU_TYPE_${ARCH} riscv32)
-
-if(CONFIG_BOARD_QEMU_RISCV32 OR CONFIG_BOARD_QEMU_RISCV32_SMP)
-  set(QEMU_FLAGS_${ARCH}
-    -nographic
-    -machine virt
-    -bios none
-    -m 256
-    )
-else()
-  set(QEMU_FLAGS_${ARCH}
-    -nographic
-    -machine sifive_e
-    )
-endif()
-
-
-board_set_debugger_ifnset(qemu)

boards/boards_legacy/riscv/qemu_riscv32/qemu_riscv32_smp.dts

@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2022 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <virt.dtsi>
-
-/ {
-	chosen {
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,sram = &ram0;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

boards/boards_legacy/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig

@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_RISCV_VIRT=y
-CONFIG_BOARD_QEMU_RISCV32_SMP=y
-CONFIG_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_UART_CONSOLE=y
-CONFIG_STACK_SENTINEL=y
-CONFIG_XIP=n
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=2
-CONFIG_QEMU_ICOUNT=n
-
-CONFIG_IDLE_STACK_SIZE=1024
-CONFIG_RISCV_PMP=y

boards/qemu/qemu_riscv32/Kconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV32
+	select QEMU_TARGET

boards/qemu/qemu_riscv32/Kconfig.defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_QEMU_RISCV32
+
+# Use thread local storage by default so that this feature gets more CI coverage.
+config THREAD_LOCAL_STORAGE
+	default y
+
+config BUILD_OUTPUT_BIN
+	default n
+
+config HAS_COVERAGE_SUPPORT
+	default y
+
+config QEMU_ICOUNT_SHIFT
+	default 6 if QEMU_ICOUNT
+
+endif # BOARD_QEMU_RISCV32

boards/qemu/qemu_riscv32/Kconfig.qemu_riscv32

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV32
+	select SOC_QEMU_VIRT_RISCV32

boards/qemu/qemu_riscv32/board.cmake

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+set(SUPPORTED_EMU_PLATFORMS qemu)
+
+set(QEMU_binary_suffix riscv32)
+set(QEMU_CPU_TYPE_${ARCH} riscv32)
+
+set(QEMU_FLAGS_${ARCH}
+  -nographic
+  -machine virt
+  -bios none
+  -m 256
+)
+
+board_set_debugger_ifnset(qemu)

boards/qemu/qemu_riscv32/board.yml

@@ -0,0 +1,7 @@
+board:
+  name: qemu_riscv32
+  vendor: qemu
+  socs:
+    - name: qemu_virt_riscv32
+      variants:
+        - name: smp

boards/qemu/qemu_riscv32/qemu_riscv32_defconfig

@@ -1,11 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_RISCV_VIRT=y
-CONFIG_BOARD_QEMU_RISCV32=y
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
 CONFIG_STACK_SENTINEL=y
-CONFIG_QEMU_ICOUNT_SHIFT=6
 CONFIG_XIP=n
 CONFIG_RISCV_PMP=y

boards/qemu/qemu_riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml

@@ -1,4 +1,4 @@
-identifier: qemu_riscv32_smp
+identifier: qemu_riscv32/qemu_virt_riscv32/smp
 name: QEMU Emulation for RISC-V 32-bit SMP
 type: qemu
 simulation: qemu

boards/qemu/qemu_riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=2
+CONFIG_IDLE_STACK_SIZE=1024
+CONFIG_QEMU_ICOUNT=n

boards/qemu/qemu_riscv32_xip/Kconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV32_XIP
+	select QEMU_TARGET

boards/qemu/qemu_riscv32_xip/Kconfig.defconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_QEMU_RISCV32_XIP
+
+# Use thread local storage by default so that this feature gets more CI coverage.
+config THREAD_LOCAL_STORAGE
+	default y
+
+config BUILD_OUTPUT_BIN
+	default n
+
+config HAS_COVERAGE_SUPPORT
+	default y
+
+endif # BOARD_QEMU_RISCV32_XIP

boards/qemu/qemu_riscv32_xip/Kconfig.qemu_riscv32_xip

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV32_XIP
+	select SOC_SIFIVE_FREEDOM_FE310

boards/qemu/qemu_riscv32_xip/board.cmake

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+set(SUPPORTED_EMU_PLATFORMS qemu)
+
+set(QEMU_binary_suffix riscv32)
+set(QEMU_CPU_TYPE_${ARCH} riscv32)
+
+set(QEMU_FLAGS_${ARCH}
+  -nographic
+  -machine sifive_e
+)
+
+board_set_debugger_ifnset(qemu)

boards/qemu/qemu_riscv32_xip/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: qemu_riscv32_xip
+  vendor: qemu
+  socs:
+    - name: fe310

boards/qemu/qemu_riscv32_xip/doc/index.rst

@@ -0,0 +1,55 @@
+.. _qemu_riscv32_xip:
+
+RISCV32 XIP Emulation (QEMU)
+############################
+
+Overview
+********
+
+The RISCV32 XIP QEMU board configuration is used to emulate the RISCV32 architecture.
+
+Programming and Debugging
+*************************
+
+Applications for the ``qemu_riscv32_xip`` board configuration can be built and run in
+the usual way for emulated boards (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+While this board is emulated and you can't "flash" it, you can use this
+configuration to run basic Zephyr applications and kernel tests in the QEMU
+emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: qemu_riscv32_xip
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it using
+QEMU, and display the following console output:
+
+.. code-block:: console
+
+   thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
+   thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
+
+Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.

boards/qemu/qemu_riscv32_xip/qemu_riscv32_xip_defconfig

@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y
-CONFIG_SOC_SIFIVE_FREEDOM_E340=y
-CONFIG_BOARD_QEMU_RISCV32_XIP=y
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_SIFIVE_PORT_0=y

tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml

@@ -11,7 +11,7 @@ tests:
       - native_posix_64
       - native_sim
       - native_sim_64
-      - qemu_riscv32_smp
+      - qemu_riscv32/qemu_virt_riscv32/smp
       - qemu_riscv64
     tags:
       - cb_notifications

tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml

@@ -37,7 +37,7 @@ tests:
       - qemu_riscv64
       - qemu_riscv32e
       - qemu_riscv32
-      - qemu_riscv32_smp
+      - qemu_riscv32/qemu_virt_riscv32/smp
       - qemu_cortex_m3
       - mps2/an385
     extra_configs: