soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2

This commit converts the virt SoC (generic virt machine) to the Zephyr
HWMv2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

soc/riscv/qemu_virt_riscv/CMakeLists.txt

@@ -1,5 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(soc.c)
-
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
+add_subdirectory(common)

soc/riscv/qemu_virt_riscv/Kconfig

@@ -1,8 +1,7 @@
-# Copyright (c) 2020 Cobham Gaisler AB
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_RISCV_VIRT
-	bool "QEMU RISC-V VirtIO Board"
+config SOC_FAMILY_QEMU_VIRT_RISCV
 	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_EXT_M
@@ -11,3 +10,9 @@ config SOC_RISCV_VIRT
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+
+if SOC_FAMILY_QEMU_VIRT_RISCV
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_QEMU_VIRT_RISCV

soc/riscv/qemu_virt_riscv/Kconfig.defconfig

@@ -1,10 +1,8 @@
 # Copyright (c) 2020 Cobham Gaisler AB
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_RISCV_VIRT
-
-config SOC
-	default "virt"
+if SOC_FAMILY_QEMU_VIRT_RISCV
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 10000000
@@ -30,4 +28,4 @@ config NUM_IRQS
 config PMP_SLOTS
 	default 16
 
-endif
+endif # SOC_FAMILY_QEMU_VIRT_RISCV

soc/riscv/qemu_virt_riscv/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_QEMU_VIRT_RISCV
+	bool
+
+config SOC_FAMILY
+	default "qemu_virt_riscv" if SOC_FAMILY_QEMU_VIRT_RISCV
+
+rsource "*/Kconfig.soc"

soc/riscv/qemu_virt_riscv/common/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)

soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32
+	select CPU_HAS_FPU
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI

soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32
+	bool
+	select SOC_FAMILY_QEMU_VIRT_RISCV
+
+config SOC
+	default "qemu_virt_riscv32" if SOC_QEMU_VIRT_RISCV32

soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Cobham Gaisler AB
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32E
+	select RISCV_ISA_RV32E
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI

soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32E
+	bool
+	select SOC_FAMILY_QEMU_VIRT_RISCV
+
+config SOC
+	default "qemu_virt_riscv32e" if SOC_QEMU_VIRT_RISCV32E

soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV64
+	select 64BIT
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI

soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV64
+	bool
+	select SOC_FAMILY_QEMU_VIRT_RISCV
+
+config SOC
+	default "qemu_virt_riscv64" if SOC_QEMU_VIRT_RISCV64

soc/riscv/qemu_virt_riscv/soc.yml

@@ -0,0 +1,6 @@
+family:
+- name: qemu_virt_riscv
+  socs:
+  - name: qemu_virt_riscv32
+  - name: qemu_virt_riscv32e
+  - name: qemu_virt_riscv64