soc: xilinx_zyncmp: Port to HWMv2

Ports the xilinx_zynqmp SoC configuration to hardware model
version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/soc_legacy/arm/xilinx_zynqmp/Kconfig

@@ -1,5 +0,0 @@
-# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_XILINX_ZYNQMP
-	bool

soc/xilinx/zynqmp/CMakeLists.txt

@@ -10,6 +10,8 @@ zephyr_sources_ifdef(
   arm_mpu_regions.c
 )
 
+zephyr_include_directories(.)
+
 if(CONFIG_SOC_XILINX_ZYNQMP_RPU)
   set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
 endif()

soc/xilinx/zynqmp/Kconfig

@@ -3,10 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_XILINX_ZYNQMP_RPU
-	bool "Xilinx ZynqMP RPU"
 	select ARM
 	select CPU_CORTEX_R5
-	select SOC_XILINX_ZYNQMP
 	select PLATFORM_SPECIFIC_INIT
 	select CPU_HAS_ARM_MPU
 	select VFP_DP_D16

soc/xilinx/zynqmp/Kconfig.defconfig

@@ -4,9 +4,6 @@
 
 if SOC_XILINX_ZYNQMP
 
-config SOC
-	default "xilinx_zynqmp"
-
 if SOC_XILINX_ZYNQMP_RPU
 
 config NUM_IRQS

soc/xilinx/zynqmp/Kconfig.soc

@@ -0,0 +1,18 @@
+# Copyright (c) 2019 Lexmark International, Inc.
+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_XILINX_ZYNQMP
+	bool
+
+config SOC_XILINX_ZYNQMP_RPU
+	bool
+	select SOC_XILINX_ZYNQMP
+	help
+	  Xilinx ZynqMP RPU
+
+config SOC_FAMILY
+	default "xilinx_zynqmp" if SOC_XILINX_ZYNQMP
+
+config SOC
+	default "zynqmp_rpu" if SOC_XILINX_ZYNQMP_RPU

soc/xilinx/zynqmp/soc.yml

@@ -0,0 +1,4 @@
+family:
+- name: xilinx_zynqmp
+  socs:
+  - name: zynqmp_rpu