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dts: arm: st: fill out adc nodes with the new properties

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Fill out all ADC nodes of all STM32 with the new properties that apply to
them.
Also moves the status at the end of each node.
Also fixes ADC2 and 3 nodes for STM32F103 and ADC3 node for STM32L471 that
were missing some required properties.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier
2025-10-07 14:10:41 +02:00
committed by Chris Friedt
parent c21cdd8569
commit 5f0c63ea35
35 changed files with 178 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
dts/arm/st/c0/stm32c0.dtsi
View File

@@ -459,7 +459,6 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 20)>;
interrupts = <12 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -469,6 +468,8 @@
num-sampling-time-common-channels = <2>;
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
status = "disabled";
};
dma1: dma@40020000 {

3
dts/arm/st/f0/stm32f0.dtsi
View File

@@ -347,7 +347,6 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <12 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -357,6 +356,8 @@
num-sampling-time-common-channels = <1>;
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dma1: dma@40020000 {

3
dts/arm/st/f1/stm32f1.dtsi
View File

@@ -394,12 +394,13 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32F1_ADC_RES(12)>;
sampling-times = <2 8 14 29 42 56 72 240>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dma1: dma@40020000 {

14
dts/arm/st/f1/stm32f103Xc.dtsi
View File

@@ -134,8 +134,13 @@
clocks = <&rcc STM32_CLOCK(APB2, 10)>;
/* Shares vector with ADC1 */
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32F1_ADC_RES(12)>;
sampling-times = <2 8 14 29 42 56 72 240>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
adc3: adc@40013c00 {
@@ -143,8 +148,13 @@
reg = <0x40013c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 15)>;
interrupts = <47 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32F1_ADC_RES(12)>;
sampling-times = <2 8 14 29 42 56 72 240>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
timers8: timers@40013400 {

3
dts/arm/st/f2/stm32f2.dtsi
View File

@@ -370,7 +370,6 @@
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 8)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -380,6 +379,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dma1: dma@40026000 {

4
dts/arm/st/f3/stm32f302.dtsi
View File

@@ -112,7 +112,6 @@
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 28)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -121,6 +120,9 @@
sampling-times = <2 3 5 8 20 62 182 602>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-differential-support;
status = "disabled";
};
};

8
dts/arm/st/f3/stm32f303.dtsi
View File

@@ -147,7 +147,6 @@
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 28)>;
interrupts = <18 0>;
status = "disabled";
vref-mv = <3000>;
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
@@ -157,6 +156,9 @@
sampling-times = <2 3 5 8 20 62 182 602>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-differential-support;
status = "disabled";
};
adc2: adc@50000100 {
@@ -164,7 +166,6 @@
reg = <0x50000100 0x4c>;
clocks = <&rcc STM32_CLOCK(AHB1, 28)>;
interrupts = <18 0>;
status = "disabled";
vref-mv = <3000>;
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
@@ -174,6 +175,9 @@
sampling-times = <2 3 5 8 20 62 182 602>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-differential-support;
status = "disabled";
};
};

4
dts/arm/st/f3/stm32f334.dtsi
View File

@@ -87,7 +87,6 @@
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 28)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -96,6 +95,9 @@
sampling-times = <2 3 5 8 20 62 182 602>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-differential-support;
status = "disabled";
};
rtc@40002800 {

3
dts/arm/st/f3/stm32f373.dtsi
View File

@@ -255,12 +255,13 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32F1_ADC_RES(12)>;
sampling-times = <2 8 14 29 42 56 72 240>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
rtc@40002800 {

3
dts/arm/st/f4/stm32f4.dtsi
View File

@@ -555,7 +555,6 @@
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 8)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -565,6 +564,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dma1: dma@40026000 {

6
dts/arm/st/f4/stm32f405.dtsi
View File

@@ -257,7 +257,6 @@
reg = <0x40012100 0x050>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -267,6 +266,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
adc3: adc@40012200 {
@@ -274,7 +275,6 @@
reg = <0x40012200 0x050>;
clocks = <&rcc STM32_CLOCK(APB2, 10)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -284,6 +284,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dac1: dac@40007400 {

6
dts/arm/st/f4/stm32f446.dtsi
View File

@@ -117,7 +117,6 @@
reg = <0x40012100 0x050>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -127,6 +126,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
adc3: adc@40012200 {
@@ -134,7 +135,6 @@
reg = <0x40012200 0x050>;
clocks = <&rcc STM32_CLOCK(APB2, 10)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -144,6 +144,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dac1: dac@40007400 {

9
dts/arm/st/f7/stm32f7.dtsi
View File

@@ -812,7 +812,6 @@
reg = <0x40012000 0x50>;
clocks = <&rcc STM32_CLOCK(APB2, 8)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -822,6 +821,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
adc2: adc@40012100 {
@@ -829,7 +830,6 @@
reg = <0x40012100 0x50>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -839,6 +839,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
adc3: adc@40012200 {
@@ -846,7 +848,6 @@
reg = <0x40012200 0x50>;
clocks = <&rcc STM32_CLOCK(APB2, 10)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -856,6 +857,8 @@
st,adc-clock-source = "SYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dac1: dac@40007400 {

3
dts/arm/st/g0/stm32g0.dtsi
View File

@@ -442,7 +442,6 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 20)>;
interrupts = <12 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -458,6 +457,8 @@
num-sampling-time-common-channels = <2>;
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
status = "disabled";
};
dma1: dma@40020000 {

10
dts/arm/st/g4/stm32g4.dtsi
View File

@@ -112,7 +112,6 @@
reg = <0x50000000 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -121,6 +120,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
adc2: adc@50000100 {
@@ -128,7 +131,6 @@
reg = <0x50000100 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -137,6 +139,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
dac1: dac@50000800 {

10
dts/arm/st/g4/stm32g473.dtsi
View File

@@ -40,7 +40,6 @@
reg = <0x50000500 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
interrupts = <61 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -49,6 +48,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
adc5: adc@50000600 {
@@ -56,7 +59,6 @@
reg = <0x50000600 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
interrupts = <62 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -65,6 +67,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
spi4: spi@40013c00 {

5
dts/arm/st/g4/stm32g491.dtsi
View File

@@ -66,7 +66,6 @@
reg = <0x50000400 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
interrupts = <47 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -75,6 +74,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
uart5: serial@40005000 {

5
dts/arm/st/h5/stm32h5.dtsi
View File

@@ -312,7 +312,6 @@
reg = <0x42028000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 10)>;
interrupts = <37 0>;
status = "disabled";
vref-mv = <3300>;
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
@@ -322,6 +321,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
rtc: rtc@44007800 {

5
dts/arm/st/h5/stm32h562.dtsi
View File

@@ -299,7 +299,6 @@
reg = <0x42028100 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 10)>;
interrupts = <69 0>;
status = "disabled";
vref-mv = <3300>;
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
@@ -309,6 +308,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
timers4: timers@40000800 {

24
dts/arm/st/h7/stm32h7.dtsi
View File

@@ -914,7 +914,6 @@
reg = <0x40022000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(16, 0x00)
STM32_ADC_RES(14, 0x05)
@@ -924,6 +923,11 @@
sampling-times = <2 3 9 17 33 65 388 811>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
st,adc-has-differential-support;
status = "disabled";
};
adc2: adc@40022100 {
@@ -931,7 +935,6 @@
reg = <0x40022100 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(16, 0x00)
STM32_ADC_RES(14, 0x05)
@@ -941,6 +944,11 @@
sampling-times = <2 3 9 17 33 65 388 811>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
st,adc-has-differential-support;
status = "disabled";
};
/* dual mode: adc1 and adc2 coupled */
@@ -949,7 +957,6 @@
reg = <0x40022300 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(16, 0x00)
STM32_ADC_RES(14, 0x05)
@@ -959,6 +966,11 @@
sampling-times = <2 3 9 17 33 65 388 811>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
st,adc-has-differential-support;
status = "disabled";
};
adc3: adc@58026000 {
@@ -966,7 +978,6 @@
reg = <0x58026000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB4, 24)>;
interrupts = <127 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(16, 0x00)
STM32_ADC_RES(14, 0x05)
@@ -976,6 +987,11 @@
sampling-times = <2 3 9 17 33 65 388 811>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
st,adc-has-differential-support;
status = "disabled";
};
dac1: dac@40007400 {

2
dts/arm/st/h7/stm32h723.dtsi
View File

@@ -53,8 +53,8 @@
STM32H72X_ADC3_RES(8, 0x02)
STM32H72X_ADC3_RES(6, 0x03)>;
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
};
dmamux1: dmamux@40020800 {

10
dts/arm/st/h7rs/stm32h7rs.dtsi
View File

@@ -812,7 +812,6 @@
reg = <0x40022000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
interrupts = <38 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -821,6 +820,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
adc2: adc@40022100 {
@@ -828,7 +831,6 @@
reg = <0x40022100 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
interrupts = <38 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -837,6 +839,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
rng: rng@48020000 {

3
dts/arm/st/l0/stm32l0.dtsi
View File

@@ -322,7 +322,6 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <12 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -332,6 +331,8 @@
num-sampling-time-common-channels = <1>;
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
status = "disabled";
};
dma1: dma@40020000 {

3
dts/arm/st/l1/stm32l1.dtsi
View File

@@ -265,7 +265,6 @@
clocks = <&rcc STM32_CLOCK(APB2, 9)>,
<&rcc STM32_SRC_HSI NO_SEL>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -275,6 +274,8 @@
st,adc-clock-source = "ASYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_NONE";
st,adc-internal-regulator = "none";
status = "disabled";
};
dac1: dac@40007400 {

10
dts/arm/st/l4/stm32l4.dtsi
View File

@@ -426,7 +426,6 @@
reg = <0x50040000 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -435,6 +434,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
adc2: adc@50040100 {
@@ -442,7 +445,6 @@
reg = <0x50040100 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -451,6 +453,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
dma1: dma@40020000 {

12
dts/arm/st/l4/stm32l471.dtsi
View File

@@ -300,8 +300,18 @@
reg = <0x50040200 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <47 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
STM32_ADC_RES(8, 0x02)
STM32_ADC_RES(6, 0x03)>;
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
rtc@40002800 {

10
dts/arm/st/l5/stm32l5.dtsi
View File

@@ -715,7 +715,6 @@
reg = <0x42028000 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <37 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -724,6 +723,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
adc2: adc@42028100 {
@@ -731,7 +734,6 @@
reg = <0x42028100 0x100>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <37 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -740,6 +742,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-deep-powerdown;
st,adc-has-differential-support;
status = "disabled";
};
fdcan1: can@4000a400 {

7
dts/arm/st/n6/stm32n6.dtsi
View File

@@ -437,7 +437,6 @@
reg = <0x50022000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
interrupts = <46 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -446,6 +445,10 @@
sampling-times = <2 3 7 12 14 47 247 1500>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "none";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
status = "disabled";
};
adc2: adc@50022100 {
@@ -453,7 +456,6 @@
reg = <0x50022100 0x300>;
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
interrupts = <46 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -462,6 +464,7 @@
sampling-times = <2 3 7 12 14 47 247 1500>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
status = "disabled";
};
fdcan1: can@5000a000 {

3
dts/arm/st/u0/stm32u0.dtsi
View File

@@ -285,7 +285,6 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 20)>;
interrupts = <12 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -295,6 +294,8 @@
num-sampling-time-common-channels = <2>;
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
status = "disabled";
};
dac1: dac@40007400 {

6
dts/arm/st/u3/stm32u3.dtsi
View File

@@ -253,6 +253,9 @@
sampling-times = <2 3 7 12 24 47 247 1500>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
status = "disabled";
};
@@ -269,6 +272,9 @@
sampling-times = <2 3 7 12 24 47 247 1500>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
status = "disabled";
};

9
dts/arm/st/u5/stm32u5.dtsi
View File

@@ -816,7 +816,6 @@
clocks = <&rcc STM32_CLOCK(AHB2, 10)>,
<&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>;
interrupts = <37 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(14, 0x00)
STM32_ADC_RES(12, 0x01)
@@ -826,6 +825,11 @@
st,adc-clock-source = "ASYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
st,adc-has-differential-support;
status = "disabled";
};
adc4: adc@46021000 {
@@ -834,7 +838,6 @@
clocks = <&rcc STM32_CLOCK(AHB3, 5)>,
<&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>;
interrupts = <113 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -845,6 +848,8 @@
st,adc-clock-source = "ASYNC";
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-hw-status";
status = "disabled";
};
fdcan1: can@4000a400 {

12
dts/arm/st/u5/stm32u595.dtsi
View File

@@ -77,7 +77,6 @@
clocks = <&rcc STM32_CLOCK(AHB2, 10)>,
<&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>;
interrupts = <37 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(14, 0x00)
STM32_ADC_RES(12, 0x01)
@@ -87,6 +86,11 @@
st,adc-clock-source = "ASYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
st,adc-has-differential-support;
status = "disabled";
};
/*
@@ -98,7 +102,6 @@
reg = <0x42028300 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 10)>;
interrupts = <37 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(14, 0x00)
STM32_ADC_RES(12, 0x01)
@@ -108,6 +111,11 @@
st,adc-clock-source = "ASYNC";
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_EXTENDED";
st,adc-internal-regulator = "startup-hw-status";
st,adc-has-deep-powerdown;
st,adc-has-channel-preselection;
st,adc-has-differential-support;
status = "disabled";
};
};

5
dts/arm/st/wb/stm32wb.dtsi
View File

@@ -425,7 +425,6 @@
reg = <0x50040000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -434,6 +433,10 @@
sampling-times = <3 7 13 25 48 93 248 641>;
st,adc-sequencer = "FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
st,adc-has-differential-support;
st,adc-has-deep-powerdown;
status = "disabled";
};
iwdg: watchdog@40003000 {

3
dts/arm/st/wba/stm32wba.dtsi
View File

@@ -494,7 +494,6 @@
clocks = <&rcc STM32_CLOCK(AHB4, 5)>,
<&rcc STM32_SRC_HCLK1 ADC_SEL(0)>;
interrupts = <65 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -505,6 +504,8 @@
st,adc-clock-source = "ASYNC";
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-hw-status";
status = "disabled";
};
lptim1: timers@46004400 {

3
dts/arm/st/wl/stm32wl.dtsi
View File

@@ -357,7 +357,6 @@
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
@@ -367,6 +366,8 @@
num-sampling-time-common-channels = <2>;
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
st,adc-internal-regulator = "startup-sw-delay";
status = "disabled";
};
dac1: dac@40007400 {