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riscv: Introduce support for RV32E

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Introduce support for RV32E.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione
2022-06-07 14:18:11 +02:00
committed by Stephanos Ioannidis
parent 737dccec1a
commit 673f41e708
8 changed files with 72 additions and 10 deletions
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12
arch/riscv/core/coredump.c
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@@ -22,12 +22,14 @@ struct riscv_arch_block {
uint32_t a3;
uint32_t a4;
uint32_t a5;
#if !defined(CONFIG_RISCV_ISA_RV32E)
uint32_t a6;
uint32_t a7;
uint32_t t3;
uint32_t t4;
uint32_t t5;
uint32_t t6;
#endif /* !CONFIG_RISCV_ISA_RV32E */
uint32_t pc;
} r;
} __packed;
@@ -62,18 +64,20 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf)
arch_blk.r.t0 = esf->t0;
arch_blk.r.t1 = esf->t1;
arch_blk.r.t2 = esf->t2;
arch_blk.r.t3 = esf->t3;
arch_blk.r.t4 = esf->t4;
arch_blk.r.t5 = esf->t5;
arch_blk.r.t6 = esf->t6;
arch_blk.r.a0 = esf->a0;
arch_blk.r.a1 = esf->a1;
arch_blk.r.a2 = esf->a2;
arch_blk.r.a3 = esf->a3;
arch_blk.r.a4 = esf->a4;
arch_blk.r.a5 = esf->a5;
#if !defined(CONFIG_RISCV_ISA_RV32E)
arch_blk.r.t3 = esf->t3;
arch_blk.r.t4 = esf->t4;
arch_blk.r.t5 = esf->t5;
arch_blk.r.t6 = esf->t6;
arch_blk.r.a6 = esf->a6;
arch_blk.r.a7 = esf->a7;
#endif /* !CONFIG_RISCV_ISA_RV32E */
arch_blk.r.pc = esf->mepc;
/* Send for output */

6
arch/riscv/core/fatal.c
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@@ -35,11 +35,17 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
LOG_ERR(" a0: " PR_REG " t0: " PR_REG, esf->a0, esf->t0);
LOG_ERR(" a1: " PR_REG " t1: " PR_REG, esf->a1, esf->t1);
LOG_ERR(" a2: " PR_REG " t2: " PR_REG, esf->a2, esf->t2);
#if defined(CONFIG_RISCV_ISA_RV32E)
LOG_ERR(" a3: " PR_REG, esf->a3);
LOG_ERR(" a4: " PR_REG, esf->a4);
LOG_ERR(" a5: " PR_REG, esf->a5);
#else
LOG_ERR(" a3: " PR_REG " t3: " PR_REG, esf->a3, esf->t3);
LOG_ERR(" a4: " PR_REG " t4: " PR_REG, esf->a4, esf->t4);
LOG_ERR(" a5: " PR_REG " t5: " PR_REG, esf->a5, esf->t5);
LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6);
LOG_ERR(" a7: " PR_REG, esf->a7);
#endif /* CONFIG_RISCV_ISA_RV32E */
#ifdef CONFIG_USERSPACE
LOG_ERR(" sp: " PR_REG, esf->sp);
#endif

24
arch/riscv/core/isr.S
View File

@@ -45,6 +45,18 @@
op t0, __z_arch_esf_t_t0_OFFSET(sp) ;\
op t1, __z_arch_esf_t_t1_OFFSET(sp)
#if defined(CONFIG_RISCV_ISA_RV32E)
#define DO_CALLER_SAVED_REST(op) \
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\
op a0, __z_arch_esf_t_a0_OFFSET(sp) ;\
op a1, __z_arch_esf_t_a1_OFFSET(sp) ;\
op a2, __z_arch_esf_t_a2_OFFSET(sp) ;\
op a3, __z_arch_esf_t_a3_OFFSET(sp) ;\
op a4, __z_arch_esf_t_a4_OFFSET(sp) ;\
op a5, __z_arch_esf_t_a5_OFFSET(sp) ;\
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
op ra, __z_arch_esf_t_ra_OFFSET(sp)
#else
#define DO_CALLER_SAVED_REST(op) \
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\
op t3, __z_arch_esf_t_t3_OFFSET(sp) ;\
@@ -61,6 +73,7 @@
op a7, __z_arch_esf_t_a7_OFFSET(sp) ;\
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
op ra, __z_arch_esf_t_ra_OFFSET(sp)
#endif /* CONFIG_RISCV_ISA_RV32E */
#ifdef CONFIG_SMP
#define GET_CURRENT_CPU(dst, tmp) \
@@ -387,7 +400,14 @@ is_user_syscall:
lr a4, __z_arch_esf_t_a4_OFFSET(sp)
lr a5, __z_arch_esf_t_a5_OFFSET(sp)
lr t0, __z_arch_esf_t_t0_OFFSET(sp)
#if defined(CONFIG_RISCV_ISA_RV32E)
/* Stack alignment for RV32E is 4 bytes */
addi sp, sp, -4
mv t1, sp
sw t1, 0(sp)
#else
mv a6, sp
#endif /* CONFIG_RISCV_ISA_RV32E */
/* validate syscall limit */
li t1, K_SYSCALL_LIMIT
@@ -408,6 +428,10 @@ valid_syscall_id:
/* Execute syscall function */
jalr ra, t2, 0
#if defined(CONFIG_RISCV_ISA_RV32E)
addi sp, sp, 4
#endif /* CONFIG_RISCV_ISA_RV32E */
/* Update a0 (return value) on the stack */
sr a0, __z_arch_esf_t_a0_OFFSET(sp)

13
arch/riscv/core/offsets/offsets.c
View File

@@ -31,6 +31,7 @@ GEN_OFFSET_SYM(_callee_saved_t, ra);
GEN_OFFSET_SYM(_callee_saved_t, tp);
GEN_OFFSET_SYM(_callee_saved_t, s0);
GEN_OFFSET_SYM(_callee_saved_t, s1);
#if !defined(CONFIG_RISCV_ISA_RV32E)
GEN_OFFSET_SYM(_callee_saved_t, s2);
GEN_OFFSET_SYM(_callee_saved_t, s3);
GEN_OFFSET_SYM(_callee_saved_t, s4);
@@ -41,6 +42,7 @@ GEN_OFFSET_SYM(_callee_saved_t, s8);
GEN_OFFSET_SYM(_callee_saved_t, s9);
GEN_OFFSET_SYM(_callee_saved_t, s10);
GEN_OFFSET_SYM(_callee_saved_t, s11);
#endif /* !CONFIG_RISCV_ISA_RV32E */
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
GEN_OFFSET_SYM(_callee_saved_t, fcsr);
@@ -63,18 +65,21 @@ GEN_OFFSET_SYM(z_arch_esf_t, ra);
GEN_OFFSET_SYM(z_arch_esf_t, t0);
GEN_OFFSET_SYM(z_arch_esf_t, t1);
GEN_OFFSET_SYM(z_arch_esf_t, t2);
GEN_OFFSET_SYM(z_arch_esf_t, t3);
GEN_OFFSET_SYM(z_arch_esf_t, t4);
GEN_OFFSET_SYM(z_arch_esf_t, t5);
GEN_OFFSET_SYM(z_arch_esf_t, t6);
GEN_OFFSET_SYM(z_arch_esf_t, a0);
GEN_OFFSET_SYM(z_arch_esf_t, a1);
GEN_OFFSET_SYM(z_arch_esf_t, a2);
GEN_OFFSET_SYM(z_arch_esf_t, a3);
GEN_OFFSET_SYM(z_arch_esf_t, a4);
GEN_OFFSET_SYM(z_arch_esf_t, a5);
#if !defined(CONFIG_RISCV_ISA_RV32E)
GEN_OFFSET_SYM(z_arch_esf_t, t3);
GEN_OFFSET_SYM(z_arch_esf_t, t4);
GEN_OFFSET_SYM(z_arch_esf_t, t5);
GEN_OFFSET_SYM(z_arch_esf_t, t6);
GEN_OFFSET_SYM(z_arch_esf_t, a6);
GEN_OFFSET_SYM(z_arch_esf_t, a7);
#endif /* !CONFIG_RISCV_ISA_RV32E */
GEN_OFFSET_SYM(z_arch_esf_t, mepc);
GEN_OFFSET_SYM(z_arch_esf_t, mstatus);

8
arch/riscv/core/switch.S
View File

@@ -14,6 +14,13 @@
/* Convenience macros for loading/storing register states. */
#if defined(CONFIG_RISCV_ISA_RV32E)
#define DO_CALLEE_SAVED(op, reg) \
op ra, _thread_offset_to_ra(reg) ;\
op tp, _thread_offset_to_tp(reg) ;\
op s0, _thread_offset_to_s0(reg) ;\
op s1, _thread_offset_to_s1(reg)
#else
#define DO_CALLEE_SAVED(op, reg) \
op ra, _thread_offset_to_ra(reg) ;\
op tp, _thread_offset_to_tp(reg) ;\
@@ -29,6 +36,7 @@
op s9, _thread_offset_to_s9(reg) ;\
op s10, _thread_offset_to_s10(reg) ;\
op s11, _thread_offset_to_s11(reg)
#endif /* CONFIG_RISCV_ISA_RV32E */
#define DO_FP_CALLEE_SAVED(op, reg) \
op fs0, _thread_offset_to_fs0(reg) ;\

11
cmake/compiler/gcc/target_riscv.cmake
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@@ -5,12 +5,19 @@ set(riscv_march "rv")
if(CONFIG_64BIT)
string(CONCAT riscv_mabi ${riscv_mabi} "64")
string(CONCAT riscv_march ${riscv_march} "64i")
string(CONCAT riscv_march ${riscv_march} "64")
list(APPEND TOOLCHAIN_C_FLAGS -mcmodel=medany)
list(APPEND TOOLCHAIN_LD_FLAGS -mcmodel=medany)
else()
string(CONCAT riscv_mabi "i" ${riscv_mabi} "32")
string(CONCAT riscv_march ${riscv_march} "32i")
string(CONCAT riscv_march ${riscv_march} "32")
endif()
if (CONFIG_RISCV_ISA_RV32E)
string(CONCAT riscv_mabi ${riscv_mabi} "e")
string(CONCAT riscv_march ${riscv_march} "e")
else()
string(CONCAT riscv_march ${riscv_march} "i")
endif()
if (CONFIG_RISCV_ISA_EXT_M)

4
include/zephyr/arch/riscv/exp.h
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@@ -55,10 +55,12 @@ struct __esf {
ulong_t t0; /* Caller-saved temporary register */
ulong_t t1; /* Caller-saved temporary register */
ulong_t t2; /* Caller-saved temporary register */
#if !defined(CONFIG_RISCV_ISA_RV32E)
ulong_t t3; /* Caller-saved temporary register */
ulong_t t4; /* Caller-saved temporary register */
ulong_t t5; /* Caller-saved temporary register */
ulong_t t6; /* Caller-saved temporary register */
#endif /* !CONFIG_RISCV_ISA_RV32E */
ulong_t a0; /* function argument/return value */
ulong_t a1; /* function argument */
@@ -66,8 +68,10 @@ struct __esf {
ulong_t a3; /* function argument */
ulong_t a4; /* function argument */
ulong_t a5; /* function argument */
#if !defined(CONFIG_RISCV_ISA_RV32E)
ulong_t a6; /* function argument */
ulong_t a7; /* function argument */
#endif /* !CONFIG_RISCV_ISA_RV32E */
ulong_t mepc; /* machine exception program counter */
ulong_t mstatus; /* machine status register */

4
include/zephyr/sys/cbprintf_internal.h
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@@ -30,7 +30,11 @@
#elif defined(__aarch64__)
#define VA_STACK_MIN_ALIGN 8
#elif defined(__riscv)
#ifdef CONFIG_RISCV_ISA_RV32E
#define VA_STACK_ALIGN(type) 4
#else
#define VA_STACK_MIN_ALIGN (__riscv_xlen / 8)
#endif /* CONFIG_RISCV_ISA_RV32E */
#endif
/*