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boards: arm: mps2: Convert to v2

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Converts the board to hwmv2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Jamie McCrae
2024-02-02 13:12:20 +00:00
parent bcf4ad19d4
commit 6ca677ed3a
45 changed files with 204 additions and 402 deletions
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18
boards/boards_legacy/arm/mps2_an521/CMakeLists.txt → boards/arm/mps2/CMakeLists.txt
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@@ -1,18 +1,13 @@
#
# Copyright (c) 2019,2020 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_library()
zephyr_library_sources(pinmux.c)
if(CONFIG_SOC_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP)
# Building a firmware image for CPU1: this requires a binary
# for CPU0, which will boot the device and wake up CPU1.
# However, if building with OPENAMP, there is no need to build
# any binary for CPU0, as this is built by the dual core sample.
if(CONFIG_BOARD_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP)
# Building a firmware image for CPU1: this requires a binary
# for CPU0, which will boot the device and wake up CPU1.
# However, if building with OPENAMP, there is no need to build
# any binary for CPU0, as this is built by the dual core sample.
set(CPU0_BINARY_DIR ${BOARD_DIR}/empty_cpu0-prefix/src/empty-cpu0-build/zephyr)
include(ExternalProject)
@@ -21,9 +16,8 @@ if(CONFIG_SOC_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP)
empty_cpu0
SOURCE_DIR ${BOARD_DIR}/empty_cpu0
INSTALL_COMMAND ""
CMAKE_CACHE_ARGS -DBOARD:STRING=mps2_an521
CMAKE_CACHE_ARGS -DBOARD:STRING=${BOARD}/an521/cpu0
BUILD_BYPRODUCTS "${CPU0_BINARY_DIR}/${KERNEL_BIN_NAME}"
BUILD_ALWAYS True
)
endif()

4
boards/boards_legacy/arm/mps2_an385/Kconfig.board → boards/arm/mps2/Kconfig
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@@ -1,8 +1,6 @@
# Copyright (c) 2017 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
config BOARD_MPS2_AN385
bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)"
depends on SOC_MPS2_AN385
config BOARD_MPS2
select QEMU_TARGET
select HAS_COVERAGE_SUPPORT

42
boards/boards_legacy/arm/mps2_an521/Kconfig.defconfig → boards/arm/mps2/Kconfig.defconfig
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@@ -1,6 +1,39 @@
# Copyright (c) 2018-2019 Linaro Limited
# Copyright (c) 2017 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
if BOARD_MPS2_AN385
if SERIAL
config UART_INTERRUPT_DRIVEN
default y
endif # SERIAL
config ZTEST_STACK_SIZE
default 4096 if ZTEST
if COVERAGE_GCOV
config MAIN_STACK_SIZE
default 4096
config IDLE_STACK_SIZE
default 4096
config PRIVILEGED_STACK_SIZE
default 4096
config ISR_STACK_SIZE
default 4096
config TEST_EXTRA_STACK_SIZE
default 4096
endif # COVERAGE_GCOV
endif
if BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1
# MPU-based null-pointer dereferencing detection cannot
@@ -9,19 +42,14 @@ if BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1
choice NULL_POINTER_EXCEPTION_DETECTION
bool
default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET
endchoice
config BOARD
default "mps2_an521_ns" if TRUSTED_EXECUTION_NONSECURE
default "mps2_an521_remote" if BOARD_MPS2_AN521_CPU1
default "mps2_an521"
endchoice
# By default, if we build for a Non-Secure version of the board,
# force building with TF-M as the Secure Execution Environment.
config BUILD_WITH_TFM
default y if TRUSTED_EXECUTION_NONSECURE
if SERIAL
config UART_INTERRUPT_DRIVEN

8
boards/arm/mps2/Kconfig.mps2 Normal file
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@@ -0,0 +1,8 @@
# Copyright (c) 2017 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
config BOARD_MPS2
select SOC_MPS2_AN385 if BOARD_MPS2_AN385
select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0
select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0_NS
select SOC_MPS2_AN521_CPU1 if BOARD_MPS2_AN521_CPU1

43
boards/arm/mps2/board.cmake Normal file
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@@ -0,0 +1,43 @@
# SPDX-License-Identifier: Apache-2.0
set(SUPPORTED_EMU_PLATFORMS qemu)
if(CONFIG_BOARD_MPS2_AN385)
set(QEMU_CPU_TYPE_${ARCH} cortex-m3)
set(QEMU_FLAGS_${ARCH}
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-machine mps2-an385
-nographic
-vga none
)
elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1)
set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
set(QEMU_FLAGS_${ARCH}
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-machine mps2-an521
-nographic
-m 16
-vga none
)
endif()
board_set_debugger_ifnset(qemu)
if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1)
# To enable a host tty switch between serial and pty
# -chardev serial,path=/dev/ttyS0,id=hostS0
list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0)
if(CONFIG_BUILD_WITH_TFM)
# Override the binary used by qemu, to use the combined
# TF-M (Secure) & Zephyr (Non Secure) image (when running
# in-tree tests).
set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex")
elseif(CONFIG_OPENAMP)
set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf")
elseif(CONFIG_BOARD_MPS2_AN521_CPU1)
set(CPU0_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr/boards/arm/mps2/empty_cpu0-prefix/src/empty_cpu0-build/zephyr)
set(QEMU_KERNEL_OPTION "-device;loader,file=${CPU0_BINARY_DIR}/zephyr.elf")
list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}")
endif()
endif()

9
boards/arm/mps2/board.yml Normal file
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@@ -0,0 +1,9 @@
board:
name: mps2
vendor: ARM
socs:
- name: an385
- name: an521
variants:
- name: ns
cpucluster: cpu0

0
boards/boards_legacy/arm/mps2_an385/doc/img/mps2_an385.jpg → boards/arm/mps2/doc/img/mps2_an385.jpg
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0
boards/boards_legacy/arm/mps2_an521/doc/img/mps2_an521.jpg → boards/arm/mps2/doc/img/mps2_an521.jpg
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13
boards/boards_legacy/arm/mps2_an385/doc/index.rst → boards/arm/mps2/doc/mps2_an385.rst
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@@ -6,7 +6,7 @@ ARM V2M MPS2
Overview
********
The mps2_an385 board configuration is used by Zephyr applications that run on
The mps2/an385 board configuration is used by Zephyr applications that run on
the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and
the following devices:
@@ -62,7 +62,7 @@ ARM V2M MPS2 provides the following hardware components:
Supported Features
==================
The mps2_an385 board configuration supports the following hardware features:
The mps2/an385 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
@@ -87,11 +87,8 @@ Other hardware features are not currently supported by the port.
See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
features.
The default configuration can be found in the defconfig file:
.. code-block:: console
boards/arm/mps2_an385/mps2_an385_defconfig
The default configuration can be found in
:zephyr_file:`boards/arm/mps2/mps2_an385_defconfig`
Interrupt Controller
====================
@@ -260,7 +257,7 @@ Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mps2_an385
:board: mps2/an385
:goals: build
Connect the V2M MPS2 to your host computer using the USB port and you should

58
boards/boards_legacy/arm/mps2_an521/doc/index.rst → boards/arm/mps2/doc/mps2_an521.rst
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@@ -6,7 +6,7 @@ ARM MPS2+ AN521
Overview
********
The mps2_an521 board configuration is used by Zephyr applications that run
The mps2/an521 board configuration is used by Zephyr applications that run
on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33
CPU and the following devices:
@@ -44,11 +44,11 @@ The BOARD options are summarized below:
+----------------------+-------------------------------------------------------+
| BOARD | Description |
+======================+=======================================================+
| mps2_an521 | For building Secure (or Secure-only) firmware on CPU0 |
| mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 |
+----------------------+-------------------------------------------------------+
| mps2_an521_ns | For building Non-Secure firmware for CPU0 |
| mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 |
+----------------------+-------------------------------------------------------+
| mps2_an521_remote | For building firmware on CPU1 |
| mps2/an521/cpu1 | For building firmware on CPU1 |
+----------------------+-------------------------------------------------------+
Memory Partitioning
@@ -63,17 +63,17 @@ The following memory map and partitioning schemes are used by default, where
the offset value is the offset from the base of the 4MB code or SRAM block,
ignoring the S/NS alias difference.
+-------------------+-----+----------------+----------------+------------+
| Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias |
+===================+=====+================+================+============+
| mps2_an521 | 0 | 4MB (0) | 4MB (0) | S |
+-------------------+-----+----------------+----------------+------------+
| mps2_an521_ns | 0 | 512KB (1MB) | 512KB (1MB) | NS |
+-------------------+-----+----------------+----------------+------------+
| mps2_an521_remote | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS |
+-------------------+-----+----------------+----------------+------------+
+-------------------------+-----+----------------+----------------+------------+
| Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias |
+=========================+=====+================+================+============+
| mps2/an521/cpu0 | 0 | 4MB (0) | 4MB (0) | S |
+-------------------------+-----+----------------+----------------+------------+
| mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS |
+-------------------------+-----+----------------+----------------+------------+
| mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS |
+-------------------------+-----+----------------+----------------+------------+
The ``mps2_an521_ns`` board target is intended to be used with TF-M, with the
The ``mps2/an521/cpu0/ns`` board target is intended to be used with TF-M, with the
Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M
boots the secure processing environment before initialising Zephyr in the
non-secure processing environment. The non-secure Zephyr image is offset to
@@ -81,7 +81,7 @@ make room for the secure bootloader, and the secure firmware (TF-M), resulting
in a starting address of 0x00100000. SRAM begins with a 1MB offset at
0x28100000.
The ``mps2_an521_remote`` board target is setup for the second core on the
The ``mps2/an521/cpu1`` board target is setup for the second core on the
AN521, using the final 468KB code memory in the 4MB code block. This value
is chosen to maintain compatibility with TF-M, which marks that final 468KB
code region as ``Unused``. Code memory thus starts with an offset of
@@ -92,9 +92,9 @@ This memory map enables the two alternative board targets to be used together
if required, at the cost of reducing the amount of code memory available on
the second core to the worst-case scenario from TF-M.
When using one of the alternative board targets (``mps2_an521_ns`` or
``mps2_an521_remote``), care needs to be taken with the amount of code or
SRAM memory used on the primary board target (``mps2_an521``) since there is
When using one of the alternative board targets (``mps2/an521/cpu0/ns`` or
``mps2/an521/cpu1``), care needs to be taken with the amount of code or
SRAM memory used on the primary board target (``mps2/an521``) since there is
some overlap in the memory maps.
Hardware
@@ -140,7 +140,7 @@ ARM MPS2+ AN521 provides the following hardware components:
User push buttons
=================
The mps2_an521 board provides the following user push buttons:
The mps2/an521 board provides the following user push buttons:
- ON power on
- nSRST: Cortex-M33 system reset and CoreSight debug reset
@@ -150,7 +150,7 @@ The mps2_an521 board provides the following user push buttons:
Supported Features
===================
The mps2_an521 board configuration supports the following hardware features:
The mps2/an521 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
@@ -175,8 +175,8 @@ Other hardware features are not currently supported by the port.
See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware
features.
The default configuration can be found in the defconfig file:
``boards/arm/mps2_an521/mps2_an521_defconfig``.
The default configuration can be found in
:zephyr_file:`boards/arm/mps2/mps2_an521_cpu0_defconfig`.
Interrupt Controller
====================
@@ -385,7 +385,7 @@ Programming and Debugging
*************************
MPS2+ AN521 (CPU0) supports the Armv8m Security Extension.
Applications built for the mps2_an521 board by default
Applications built for the mps2/an521 board by default
boot in the Secure state.
MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension.
@@ -410,7 +410,7 @@ The process to build the Secure firmware image using TF-M and the Non-Secure
firmware image using Zephyr requires the following steps:
1. Build the Non-Secure Zephyr application
for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2_an521_ns``.
for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2/an521/cpu0/ns``.
To invoke the building of TF-M the Zephyr build system requires the
Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by
default when building Zephyr as a Non-Secure application.
@@ -434,18 +434,18 @@ The process to build the Secure and the Non-Secure firmware images
using Zephyr requires the following steps:
1. Build the Secure Zephyr application for MPS2+ AN521 (CPU0)
using ``-DBOARD=mps2_an521`` and
using ``-DBOARD=mps2/an521`` and
``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n``
in the application project configuration file.
2. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0)
using ``-DBOARD=mps2_an521_ns``.
using ``-DBOARD=mps2/an521/cpu0/ns``.
3. Merge the two binaries together.
Building a Secure only application on MPS2+ AN521 (CPU0)
========================================================
Build the Zephyr app in the usual way (see :ref:`build_an_application`
and :ref:`application_run`), using ``-DBOARD=mps2_an521`` for
and :ref:`application_run`), using ``-DBOARD=mps2/an521`` for
the firmware running on the MPS2+ AN521 (CPU0).
When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0),
@@ -472,7 +472,7 @@ Applications may be built for the second Cortex-M33
(remote) core of MPS2+ AN521. The core is referred to as CPU1.
Build the Zephyr app in the usual way (see :ref:`build_an_application`
and :ref:`application_run`), using ``-DBOARD=mps2_an521_remote`` for
and :ref:`application_run`), using ``-DBOARD=mps2/an521/cpu1`` for
the firmware running on the MPS2+ AN521 (CPU1).
The Zephyr build will automatically trigger building a minimal (empty)
@@ -494,7 +494,7 @@ a secure-only application for CPU0.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mps2_an521
:board: mps2/an521
:goals: build

0
boards/boards_legacy/arm/mps2_an521/empty_cpu0/CMakeLists.txt → boards/arm/mps2/empty_cpu0/CMakeLists.txt
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0
boards/boards_legacy/arm/mps2_an521/empty_cpu0/prj.conf → boards/arm/mps2/empty_cpu0/prj.conf
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0
boards/boards_legacy/arm/mps2_an521/empty_cpu0/src/main.c → boards/arm/mps2/empty_cpu0/src/main.c
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0
boards/boards_legacy/arm/mps2_an385/mps2_an385.dts → boards/arm/mps2/mps2_an385.dts
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2
boards/boards_legacy/arm/mps2_an385/mps2_an385.yaml → boards/arm/mps2/mps2_an385.yaml
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@@ -1,4 +1,4 @@
identifier: mps2_an385
identifier: mps2/an385
name: ARM V2M MPS2
type: mcu
arch: arm

3
boards/boards_legacy/arm/mps2_an385/mps2_an385_defconfig → boards/arm/mps2/mps2_an385_defconfig
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@@ -4,9 +4,6 @@
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SOC_SERIES_MPS2=y
CONFIG_SOC_MPS2_AN385=y
CONFIG_BOARD_MPS2_AN385=y
CONFIG_RUNTIME_NMI=y
CONFIG_QEMU_ICOUNT_SHIFT=7

0
boards/boards_legacy/arm/mps2_an521/mps2_an521-common.dtsi → boards/arm/mps2/mps2_an521-common.dtsi
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0
boards/boards_legacy/arm/mps2_an521/mps2_an521.dts → boards/arm/mps2/mps2_an521_cpu0.dts
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2
boards/boards_legacy/arm/mps2_an521/mps2_an521.yaml → boards/arm/mps2/mps2_an521_cpu0.yaml
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@@ -1,4 +1,4 @@
identifier: mps2_an521
identifier: mps2/an521/cpu0
name: ARM V2M MPS2-AN521
type: mcu
arch: arm

3
boards/boards_legacy/arm/mps2_an521/mps2_an521_defconfig → boards/arm/mps2/mps2_an521_cpu0_defconfig
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@@ -4,9 +4,6 @@
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SOC_SERIES_MPS2=y
CONFIG_SOC_MPS2_AN521_CPU0=y
CONFIG_BOARD_MPS2_AN521_CPU0=y
CONFIG_RUNTIME_NMI=y
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_ARM_MPU=y

0
boards/boards_legacy/arm/mps2_an521/mps2_an521_ns.dts → boards/arm/mps2/mps2_an521_cpu0_ns.dts
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2
boards/boards_legacy/arm/mps2_an521/mps2_an521_ns.yaml → boards/arm/mps2/mps2_an521_cpu0_ns.yaml
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@@ -1,4 +1,4 @@
identifier: mps2_an521_ns
identifier: mps2/an521/cpu0/ns
name: ARM V2M MPS2-AN521_ns
type: mcu
arch: arm

11
boards/arm/mps2/mps2_an521_cpu0_ns_defconfig Normal file
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@@ -0,0 +1,11 @@
#
# Copyright (c) 2018-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_QEMU_ICOUNT_SHIFT=6
# Build a non-secure firmware image
CONFIG_TRUSTED_EXECUTION_SECURE=n
CONFIG_TRUSTED_EXECUTION_NONSECURE=y

0
boards/boards_legacy/arm/mps2_an521/mps2_an521_remote.dts → boards/arm/mps2/mps2_an521_cpu1.dts
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4
boards/boards_legacy/arm/mps2_an521/mps2_an521_remote.yaml → boards/arm/mps2/mps2_an521_cpu1.yaml
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@@ -1,5 +1,5 @@
identifier: mps2_an521_remote
name: ARM V2M MPS2-AN521_remote
identifier: mps2/an521/cpu1
name: ARM V2M MPS2-AN521_cpu1
type: mcu
arch: arm
ram: 512

3
boards/boards_legacy/arm/mps2_an521/mps2_an521_remote_defconfig → boards/arm/mps2/mps2_an521_cpu1_defconfig
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@@ -5,9 +5,6 @@
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SOC_SERIES_MPS2=y
CONFIG_SOC_MPS2_AN521_CPU1=y
CONFIG_BOARD_MPS2_AN521_CPU1=y
CONFIG_RUNTIME_NMI=y
CONFIG_ARM_MPU=y
CONFIG_QEMU_ICOUNT_SHIFT=7

0
boards/boards_legacy/arm/mps2_an385/pinmux.c → boards/arm/mps2/pinmux.c
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4
boards/boards_legacy/arm/mps2_an385/CMakeLists.txt
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@@ -1,4 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_library()
zephyr_library_sources(pinmux.c)

38
boards/boards_legacy/arm/mps2_an385/Kconfig.defconfig
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@@ -1,38 +0,0 @@
# Copyright (c) 2017 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
if BOARD_MPS2_AN385
config BOARD
default "mps2_an385"
if SERIAL
config UART_INTERRUPT_DRIVEN
default y
endif # SERIAL
config ZTEST_STACK_SIZE
default 4096 if ZTEST
if COVERAGE_GCOV
config MAIN_STACK_SIZE
default 4096
config IDLE_STACK_SIZE
default 4096
config PRIVILEGED_STACK_SIZE
default 4096
config ISR_STACK_SIZE
default 4096
config TEST_EXTRA_STACK_SIZE
default 4096
endif # COVERAGE_GCOV
endif

13
boards/boards_legacy/arm/mps2_an385/board.cmake
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@@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_CPU_TYPE_${ARCH} cortex-m3)
set(QEMU_FLAGS_${ARCH}
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-machine mps2-an385
-nographic
-vga none
)
board_set_debugger_ifnset(qemu)

20
boards/boards_legacy/arm/mps2_an521/Kconfig.board
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@@ -1,20 +0,0 @@
# Copyright (c) 2018-2019 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
config BOARD_MPS2_AN521_CPU0
bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0)"
depends on SOC_MPS2_AN521_CPU0
select QEMU_TARGET
select HAS_COVERAGE_SUPPORT
config BOARD_MPS2_AN521_CPU0_NS
bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0 Non-Secure)"
depends on SOC_MPS2_AN521_CPU0
select QEMU_TARGET
select HAS_COVERAGE_SUPPORT
config BOARD_MPS2_AN521_CPU1
bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) CPU1"
depends on SOC_MPS2_AN521_CPU1
select QEMU_TARGET
select HAS_COVERAGE_SUPPORT

33
boards/boards_legacy/arm/mps2_an521/board.cmake
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@@ -1,33 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
set(QEMU_FLAGS_${ARCH}
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-machine mps2-an521
-nographic
-m 16
-vga none
)
board_set_debugger_ifnset(qemu)
board_runner_args(pyocd "--target=mps2_an521")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
# To enable a host tty switch between serial and pty
# -chardev serial,path=/dev/ttyS0,id=hostS0
list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0)
if (CONFIG_BUILD_WITH_TFM)
# Override the binary used by qemu, to use the combined
# TF-M (Secure) & Zephyr (Non Secure) image (when running
# in-tree tests).
set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex")
elseif(CONFIG_OPENAMP)
set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf")
elseif (CONFIG_SOC_MPS2_AN521_CPU1)
set(CPU0_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr/boards/arm/mps2_an521/empty_cpu0-prefix/src/empty_cpu0-build/zephyr)
set(QEMU_KERNEL_OPTION "-device;loader,file=${CPU0_BINARY_DIR}/zephyr.elf")
list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}")
endif()

22
boards/boards_legacy/arm/mps2_an521/mps2_an521_ns_defconfig
View File

@@ -1,22 +0,0 @@
#
# Copyright (c) 2018-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SOC_SERIES_MPS2=y
CONFIG_SOC_MPS2_AN521_CPU0=y
CONFIG_BOARD_MPS2_AN521_CPU0_NS=y
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_RUNTIME_NMI=y
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
CONFIG_ARM_MPU=y
CONFIG_QEMU_ICOUNT_SHIFT=6
# GPIOs
CONFIG_GPIO=y
# Serial
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y

164
boards/boards_legacy/arm/mps2_an521/pinmux.c
View File

@@ -1,164 +0,0 @@
/*
* Copyright (c) 2018-2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/drivers/gpio/gpio_cmsdk_ahb.h>
/**
* @brief Pinmux driver for ARM MPS2 AN521 Board
*
* The ARM MPS2 AN521 Board has 4 GPIO controllers. These controllers
* are responsible for pin muxing, input/output, pull-up, etc.
*
* All GPIO controller pins are exposed via the following sequence of pin
* numbers:
* Pins 0 - 15 are for GPIO0
* Pins 16 - 31 are for GPIO1
* Pins 32 - 47 are for GPIO2
* Pins 48 - 51 are for GPIO3
*
* For the GPIO controllers configuration ARM MPS2 AN521 Board follows the
* Arduino compliant pin out.
*/
#define CMSDK_AHB_GPIO0_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0)))
#define CMSDK_AHB_GPIO1_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1)))
#define CMSDK_AHB_GPIO2_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2)))
#define CMSDK_AHB_GPIO3_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3)))
/*
* This is the mapping from the ARM MPS2 AN521 Board pins to GPIO
* controllers.
*
* D0 : EXT_0
* D1 : EXT_4
* D2 : EXT_2
* D3 : EXT_3
* D4 : EXT_1
* D5 : EXT_6
* D6 : EXT_7
* D7 : EXT_8
* D8 : EXT_9
* D9 : EXT_10
* D10 : EXT_12
* D11 : EXT_13
* D12 : EXT_14
* D13 : EXT_11
* D14 : EXT_15
* D15 : EXT_5
* D16 : EXT_16
* D17 : EXT_17
* D18 : EXT_18
* D19 : EXT_19
* D20 : EXT_20
* D21 : EXT_21
* D22 : EXT_22
* D23 : EXT_23
* D24 : EXT_24
* D25 : EXT_25
* D26 : EXT_26
* D27 : EXT_30
* D28 : EXT_28
* D29 : EXT_29
* D30 : EXT_27
* D31 : EXT_32
* D32 : EXT_33
* D33 : EXT_34
* D34 : EXT_35
* D35 : EXT_36
* D36 : EXT_38
* D37 : EXT_39
* D38 : EXT_40
* D39 : EXT_44
* D40 : EXT_41
* D41 : EXT_31
* D42 : EXT_37
* D43 : EXT_42
* D44 : EXT_43
* D45 : EXT_45
* D46 : EXT_46
* D47 : EXT_47
* D48 : EXT_48
* D49 : EXT_49
* D50 : EXT_50
* D51 : EXT_51
*
* UART_3_RX : D0
* UART_3_TX : D1
* SPI_3_CS : D10
* SPI_3_MOSI : D11
* SPI_3_MISO : D12
* SPI_3_SCLK : D13
* I2C_3_SDA : D14
* I2C_3_SCL : D15
* UART_4_RX : D26
* UART_4_TX : D30
* SPI_4_CS : D36
* SPI_4_MOSI : D37
* SPI_4_MISO : D38
* SPI_4_SCK : D39
* I2C_4_SDA : D40
* I2C_4_SCL : D41
*
*/
static void arm_mps2_pinmux_defaults(void)
{
uint32_t gpio_0 = 0;
uint32_t gpio_1 = 0;
uint32_t gpio_2 = 0;
/* Set GPIO Alternate Functions */
gpio_0 = (1<<0) /* Shield 0 UART 3 RXD */
| (1<<4) /* Shield 0 UART 3 TXD */
| (1<<5) /* Shield 0 I2C SCL SBCON2 */
| (1<<15) /* Shield 0 I2C SDA SBCON2 */
| (1<<11) /* Shield 0 SPI 3 SCK */
| (1<<12) /* Shield 0 SPI 3 SS */
| (1<<13) /* Shield 0 SPI 3 MOSI */
| (1<<14); /* Shield 0 SPI 3 MISO */
CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0;
gpio_1 = (1<<10) /* Shield 1 UART 4 RXD */
| (1<<14) /* Shield 1 UART 4 TXD */
| (1<<15) /* Shield 1 I2C SCL SBCON3 */
| (1<<0) /* ADC SPI 2 SS */
| (1<<1) /* ADC SPI 2 MISO */
| (1<<2) /* ADC SPI 2 MOSI */
| (1<<3) /* ADC SPI 2 SCK */
| (1<<5) /* USER BUTTON 0 */
| (1<<6); /* USER BUTTON 1 */
CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1;
gpio_2 = (1<<9) /* Shield 1 I2C SDA SBCON3 */
| (1<<6) /* Shield 1 SPI 4 SS */
| (1<<7) /* Shield 1 SPI 4 MOSI */
| (1<<8) /* Shield 1 SPI 4 MISO */
| (1<<12); /* Shield 1 SPI 4 SCK */
CMSDK_AHB_GPIO2_DEV->altfuncset = gpio_2;
}
static int arm_mps2_pinmux_init(void)
{
arm_mps2_pinmux_defaults();
return 0;
}
SYS_INIT(arm_mps2_pinmux_init, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

6
soc/soc_legacy/arm/arm/mps2/CMakeLists.txt → soc/arm/mps2/CMakeLists.txt
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
soc.c
)
zephyr_sources(soc.c)
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

16
soc/soc_legacy/arm/arm/mps2/Kconfig.soc → soc/arm/mps2/Kconfig
View File

@@ -1,29 +1,21 @@
# Copyright (c) 2017-2019 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MPS2
select ARM
select GPIO_MMIO32 if GPIO
config SOC_MPS2_AN521
bool
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
choice
prompt "ARM MPS2 SoCs"
depends on SOC_SERIES_MPS2
config SOC_MPS2_AN385
bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)"
select CPU_CORTEX_M3
select CPU_HAS_ARM_MPU
config SOC_MPS2_AN521_CPU0
bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0"
select SOC_MPS2_AN521
select CPU_HAS_ARM_SAU
config SOC_MPS2_AN521_CPU1
bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1"
select SOC_MPS2_AN521
select CPU_HAS_FPU
select ARMV8_M_DSP
endchoice

5
soc/soc_legacy/arm/arm/mps2/Kconfig.defconfig.series → soc/arm/mps2/Kconfig.defconfig
View File

@@ -3,12 +3,9 @@
if SOC_SERIES_MPS2
config SOC_SERIES
default "mps2"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 25000000
source "soc/soc_legacy/arm/arm/mps2/Kconfig.defconfig.mps2*"
rsource "Kconfig.defconfig.*"
endif # SOC_SERIES_MPS2

3
soc/soc_legacy/arm/arm/mps2/Kconfig.defconfig.mps2_an385 → soc/arm/mps2/Kconfig.defconfig.an385
View File

@@ -3,9 +3,6 @@
if SOC_MPS2_AN385
config SOC
default "mps2_an385"
config NUM_IRQS
default 32

3
soc/soc_legacy/arm/arm/mps2/Kconfig.defconfig.mps2_an521 → soc/arm/mps2/Kconfig.defconfig.an521
View File

@@ -3,9 +3,6 @@
if SOC_MPS2_AN521
config SOC
default "mps2_an521"
config NUM_IRQS
default 96

37
soc/arm/mps2/Kconfig.soc Normal file
View File

@@ -0,0 +1,37 @@
# Copyright (c) 2017-2019 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MPS2
bool
select SOC_FAMILY_ARM
help
Enable support for ARM MPS2 MCU Series
config SOC_MPS2_AN385
bool
select SOC_SERIES_MPS2
help
ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)
config SOC_MPS2_AN521
bool
select SOC_SERIES_MPS2
config SOC_MPS2_AN521_CPU0
bool
select SOC_MPS2_AN521
help
ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0
config SOC_MPS2_AN521_CPU1
bool
select SOC_MPS2_AN521
help
ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1
config SOC_SERIES
default "mps2" if SOC_SERIES_MPS2
config SOC
default "an385" if SOC_MPS2_AN385
default "an521" if SOC_MPS2_AN521

0
soc/soc_legacy/arm/arm/mps2/soc.c → soc/arm/mps2/soc.c
View File

0
soc/soc_legacy/arm/arm/mps2/soc.h → soc/arm/mps2/soc.h
View File

0
soc/soc_legacy/arm/arm/mps2/soc_registers.h → soc/arm/mps2/soc_registers.h
View File

7
soc/arm/soc.yml
View File

@@ -1,6 +1,13 @@
family:
- name: arm
series:
- name: mps2
socs:
- name: an385
- name: an521
cpuclusters:
- name: cpu0
- name: cpu1
- name: mps3
socs:
- name: an547

10
soc/soc_legacy/arm/arm/mps2/Kconfig.series
View File

@@ -1,10 +0,0 @@
# Copyright (c) 2017 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MPS2
bool "Arm MPS2 MCU Series"
select ARM
select SOC_FAMILY_ARM
select GPIO_MMIO32 if GPIO
help
Enable support for ARM MPS2 MCU Series