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tests: Update to use SOC_SERIES_NRF Kconfigs without X suffix

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Updates usage of the old Kconfig to use the new Kconfig

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Jamie McCrae
2026-01-15 09:04:05 +00:00
committed by Fabio Baltieri
parent 9700579f6a
commit 70fcffd5de
11 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
tests/application_development/ram_context_for_isr/Kconfig
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@@ -12,7 +12,7 @@ config TEST_IRQ_NUM
default 18 if SOC_SERIES_STM32C0X
default 1 if (SOC_SERIES_NPCX9 || SOC_SERIES_NPCX7 || SOC_SERIES_NPCK3)
default 29 if SOC_K32L2B31A
default 28 if SOC_SERIES_NRF54LX
default 28 if SOC_SERIES_NRF54L
default 0
help
IRQ number to use for testing purposes. This should be an

12
tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
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@@ -24,10 +24,10 @@
* the TIMER0 IRQ line, which is used by the system timer.
*/
#define _ISR_OFFSET (TIMER0_IRQn + 1)
#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF71)
#elif defined(CONFIG_SOC_SERIES_NRF54L) || defined(CONFIG_SOC_SERIES_NRF71)
/* For nRF54L Series, use SWI00-02 interrupt lines. */
#define _ISR_OFFSET SWI00_IRQn
#elif defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF92X)
#elif defined(CONFIG_SOC_SERIES_NRF54H) || defined(CONFIG_SOC_SERIES_NRF92)
/* For nRF54H and nRF92 Series, use BELLBOARD_0-2 interrupt lines. */
#define _ISR_OFFSET BELLBOARD_0_IRQn
#else
@@ -144,9 +144,9 @@ typedef void (*vth)(void); /* Vector Table Handler */
* Note: qemu_cortex_m0 uses TIMER0 to implement system timer.
*/
void nrfx_power_clock_irq_handler(void);
#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)
#if defined(CONFIG_SOC_SERIES_NRF51) || defined(CONFIG_SOC_SERIES_NRF52)
#define POWER_CLOCK_IRQ_NUM POWER_CLOCK_IRQn
#elif defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF92X)
#elif defined(CONFIG_SOC_SERIES_NRF54H) || defined(CONFIG_SOC_SERIES_NRF92)
#define POWER_CLOCK_IRQ_NUM -1 /* not needed */
#else
#define POWER_CLOCK_IRQ_NUM CLOCK_POWER_IRQn
@@ -156,8 +156,8 @@ void nrfx_power_clock_irq_handler(void);
void timer0_nrf_isr(void);
#define TIMER_IRQ_HANDLER timer0_nrf_isr
#define TIMER_IRQ_NUM TIMER0_IRQn
#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF54HX) || \
defined(CONFIG_SOC_SERIES_NRF71) || defined(CONFIG_SOC_SERIES_NRF92X)
#elif defined(CONFIG_SOC_SERIES_NRF54L) || defined(CONFIG_SOC_SERIES_NRF54H) || \
defined(CONFIG_SOC_SERIES_NRF71) || defined(CONFIG_SOC_SERIES_NRF92)
void nrfx_grtc_irq_handler(void);
#define TIMER_IRQ_HANDLER nrfx_grtc_irq_handler
#define TIMER_IRQ_NUM DT_IRQN(DT_NODELABEL(grtc))

6
tests/arch/common/gen_isr_table/src/main.c
View File

@@ -31,13 +31,13 @@ extern const uintptr_t _irq_vector_table[];
#if defined(CONFIG_NRFX_CLIC)
#if (defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_NRF54H20_CPUFLPR)) && \
#if (defined(CONFIG_SOC_SERIES_NRF54L) || defined(CONFIG_SOC_NRF54H20_CPUFLPR)) && \
defined(CONFIG_RISCV_CORE_NORDIC_VPR)
#define ISR1_OFFSET 16
#define ISR3_OFFSET 17
#define ISR5_OFFSET 18
#define TRIG_CHECK_SIZE 19
#elif defined(CONFIG_SOC_SERIES_NRF54HX) && defined(CONFIG_RISCV_CORE_NORDIC_VPR)
#elif defined(CONFIG_SOC_SERIES_NRF54H) && defined(CONFIG_RISCV_CORE_NORDIC_VPR)
#define ISR1_OFFSET 14
#define ISR3_OFFSET 15
#define ISR5_OFFSET 16
@@ -110,7 +110,7 @@ extern const uintptr_t _irq_vector_table[];
* with isr used here, so add a workaround
*/
#define TEST_NUM_IRQS 105
#elif defined(CONFIG_SOC_NRF5340_CPUAPP) || defined(CONFIG_SOC_SERIES_NRF91X)
#elif defined(CONFIG_SOC_NRF5340_CPUAPP) || defined(CONFIG_SOC_SERIES_NRF91)
/* In the application core of nRF5340 and nRF9 series, not all interrupts with highest
* numbers are implemented. Thus, limit the number of interrupts reported to
* the test, so that it does not try to use some unavailable ones.

4
tests/arch/common/interrupt/src/nested_irq.c
View File

@@ -62,14 +62,14 @@
*/
#define IRQ0_PRIO IRQ_DEFAULT_PRIORITY
#define IRQ1_PRIO 0x0
#elif (defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_NRF54H20_CPUFLPR)) && \
#elif (defined(CONFIG_SOC_SERIES_NRF54L) || defined(CONFIG_SOC_NRF54H20_CPUFLPR)) && \
defined(CONFIG_RISCV_CORE_NORDIC_VPR)
#define IRQ0_LINE 16
#define IRQ1_LINE 17
#define IRQ0_PRIO 1
#define IRQ1_PRIO 2
#elif defined(CONFIG_SOC_SERIES_NRF54HX) && defined(CONFIG_RISCV_CORE_NORDIC_VPR)
#elif defined(CONFIG_SOC_SERIES_NRF54H) && defined(CONFIG_RISCV_CORE_NORDIC_VPR)
#define IRQ0_LINE 14
#define IRQ1_LINE 15

2
tests/drivers/clock_control/clock_control_api/Kconfig
View File

@@ -3,7 +3,7 @@
config TEST_NRF_HF_STARTUP_TIME_US
int "Delay required for HF clock startup."
default 3000 if SOC_SERIES_NRF91X
default 3000 if SOC_SERIES_NRF91
default 500
depends on SOC_FAMILY_NORDIC_NRF
help

2
tests/drivers/clock_control/nrf_onoff_and_bt/src/main.c
View File

@@ -14,7 +14,7 @@ LOG_MODULE_REGISTER(test);
#define TEST_TIME_MS 10000
#ifdef CONFIG_SOC_SERIES_NRF54LX
#ifdef CONFIG_SOC_SERIES_NRF54L
#define HF_STARTUP_TIME_US 600
#else
#define HF_STARTUP_TIME_US 400

2
tests/drivers/flash/negative_tests/src/main.c
View File

@@ -26,7 +26,7 @@
#define TEST_AREA_SIZE FIXED_PARTITION_SIZE(TEST_AREA)
#define TEST_AREA_DEVICE FIXED_PARTITION_DEVICE(TEST_AREA)
#if defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_FAMILY_MICROCHIP_SAM_D5X_E5X)
#if defined(CONFIG_SOC_SERIES_NRF54L) || defined(CONFIG_SOC_FAMILY_MICROCHIP_SAM_D5X_E5X)
#define TEST_FLASH_START (DT_REG_ADDR(DT_MEM_FROM_FIXED_PARTITION(DT_NODELABEL(TEST_AREA))))
#define TEST_FLASH_SIZE (DT_REG_SIZE(DT_MEM_FROM_FIXED_PARTITION(DT_NODELABEL(TEST_AREA))))
#elif defined(CONFIG_SOC_NRF54H20)

2
tests/drivers/watchdog/wdt_error_cases/src/main.c
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@@ -44,7 +44,7 @@
#define DEFAULT_WINDOW_MIN (0U)
/* Align tests to the specific target: */
#if defined(CONFIG_SOC_SERIES_NRF53X) || defined(CONFIG_SOC_SERIES_NRF54LX) || \
#if defined(CONFIG_SOC_SERIES_NRF53) || defined(CONFIG_SOC_SERIES_NRF54L) || \
defined(CONFIG_SOC_SERIES_NRF71) || defined(CONFIG_SOC_NRF54H20) || \
defined(CONFIG_SOC_NRF9280)
#define WDT_TEST_FLAGS \

2
tests/kernel/sleep/src/usleep.c
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@@ -28,7 +28,7 @@
/* The overhead of k_usleep() adds three ticks per loop iteration on
* nRF51, which has a slow CPU clock.
*/
#define MAXIMUM_SHORTEST_TICKS (IS_ENABLED(CONFIG_SOC_SERIES_NRF51X) ? 6 : 3)
#define MAXIMUM_SHORTEST_TICKS (IS_ENABLED(CONFIG_SOC_SERIES_NRF51) ? 6 : 3)
/* Similar situation for TI CC13XX/CC26XX RTC kernel timer due to the
* limitation that a value too close to the current time cannot be
* loaded to its comparator.

2
tests/lib/cpp/cxx/testcase.yaml
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@@ -44,7 +44,7 @@ tests:
not CONFIG_HAS_SILABS_WISECONNECT and
not CONFIG_SOC_FAMILY_AMBIQ and
not (CONFIG_CPU_CORTEX_M and (CONFIG_NRF_PLATFORM_HALTIUM or
CONFIG_SOC_SERIES_NRF54LX or CONFIG_SOC_SERIES_NRF71))
CONFIG_SOC_SERIES_NRF54L or CONFIG_SOC_SERIES_NRF71))
build_only: true
extra_configs:
- CONFIG_STD_CPP98=y

4
tests/lib/mpsc_pbuf/src/main.c
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@@ -95,7 +95,7 @@ static void init(struct mpsc_pbuf_buffer *buffer, uint32_t wlen, bool overwrite)
mpsc_buf_cfg.size = wlen;
mpsc_pbuf_init(buffer, &mpsc_buf_cfg);
#if CONFIG_SOC_SERIES_NRF52X
#if CONFIG_SOC_SERIES_NRF52
DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk;
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
DWT->CYCCNT = 0;
@@ -104,7 +104,7 @@ static void init(struct mpsc_pbuf_buffer *buffer, uint32_t wlen, bool overwrite)
static inline uint32_t get_cyc(void)
{
#if CONFIG_SOC_SERIES_NRF52X
#if CONFIG_SOC_SERIES_NRF52
return DWT->CYCCNT;
#else
return k_cycle_get_32();