From 8402a4f8e5b49c09f65bbfb7d93164375eceaf4b Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Wed, 21 Jan 2026 11:17:47 +0100 Subject: [PATCH] drivers: gpio: mcux: Fix updating ICR registers without IRQ lock During configuration the base->ICR1 or base->ICR2 register is written without an IRQ lock. This can result in unwanted side-effects if the status bit isn't cleared, or the edge select still needs to be updated. Signed-off-by: Pieter De Gendt --- drivers/gpio/gpio_mcux_igpio.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c index f55df0746ae..6e0240d9d5d 100644 --- a/drivers/gpio/gpio_mcux_igpio.c +++ b/drivers/gpio/gpio_mcux_igpio.c @@ -292,6 +292,10 @@ static int mcux_igpio_pin_interrupt_configure(const struct device *dev, return -ENOTSUP; } + if (pin >= 32) { + return -EINVAL; + } + if (mode == GPIO_INT_MODE_DISABLED) { key = irq_lock(); @@ -314,18 +318,16 @@ static int mcux_igpio_pin_interrupt_configure(const struct device *dev, icr = 0; } + key = irq_lock(); + if (pin < 16) { shift = 2 * pin; base->ICR1 = (base->ICR1 & ~(3 << shift)) | (icr << shift); - } else if (pin < 32) { + } else { shift = 2 * (pin - 16); base->ICR2 = (base->ICR2 & ~(3 << shift)) | (icr << shift); - } else { - return -EINVAL; } - key = irq_lock(); - WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH); WRITE_BIT(base->ISR, pin, 1); WRITE_BIT(base->IMR, pin, 1);