michael/zephyr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

tests: clock_control: stm32h7: pll2: Fix test configuration

Browse Source 
In test spi1_pll2p_1, pll2 should be enabled instead of pll3.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
2022-12-21 15:53:44 +01:00
committed by Carles Cufí
parent a7743a49aa
commit 888607d550
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay
View File

@@ -9,7 +9,7 @@
* It is assumed that it is applied after core_init.overlay file.
*/
&pll3 {
&pll2 {
clocks = <&clk_hse>;
div-m = <1>;
mul-n = <24>;