soc: gigadevice: port to HWMv2

Port all the Gigadevice SoCs to HWMv2.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

samples/drivers/watchdog/sample.yaml

@@ -16,7 +16,7 @@ common:
   depends_on: watchdog
 tests:
   sample.drivers.watchdog:
-    filter: not (CONFIG_SOC_FAMILY_STM32 or CONFIG_SOC_FAMILY_GD32 or SOC_SERIES_GD32VF103)
+    filter: not (CONFIG_SOC_FAMILY_STM32 or CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103)
     platform_exclude:
       - s32z270dc2_rtu0_r52
       - s32z270dc2_rtu1_r52

soc/arm/gd_gd32/Kconfig

@@ -1,23 +0,0 @@
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_GD32
-	bool
-	select HAS_GD32_HAL
-	select BUILD_OUTPUT_HEX
-	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
-
-config SOC_FAMILY
-	string
-	default "gd_gd32"
-	depends on SOC_FAMILY_GD32
-
-config SOC_FAMILY_GD32_ARM
-	bool
-	select SOC_FAMILY_GD32
-
-if SOC_FAMILY_GD32_ARM
-
-source "soc/arm/gd_gd32/*/Kconfig.soc"
-
-endif # SOC_FAMILY_GD32_ARM

soc/arm/gd_gd32/Kconfig.soc

@@ -1,4 +0,0 @@
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/arm/gd_gd32/*/Kconfig.series"

soc/arm/gd_gd32/gd32a50x/Kconfig.soc

@@ -1,11 +0,0 @@
-# Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32A50X MCU Selection"
-	depends on SOC_SERIES_GD32A50X
-
-	config SOC_GD32A503
-		bool "gd32a503"
-
-endchoice

soc/arm/gd_gd32/gd32e10x/Kconfig.soc

@@ -1,10 +0,0 @@
-# Copyright (c) 2021 YuLong Yao <feilongphone@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32E103 MCU Selection"
-	depends on SOC_SERIES_GD32E10X
-
-	config SOC_GD32E103
-		bool "gd32e103"
-endchoice

soc/arm/gd_gd32/gd32e50x/Kconfig.soc

@@ -1,11 +0,0 @@
-# Copyright (c) 2022, Teslabs Engineering S.L.
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32E50X MCU Selection"
-	depends on SOC_SERIES_GD32E50X
-
-	config SOC_GD32E507
-		bool "gd32e507"
-
-endchoice

soc/arm/gd_gd32/gd32f3x0/Kconfig.soc

@@ -1,10 +0,0 @@
-# Copyright (c) 2021 BrainCo Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32F3X0 MCU Selection"
-	depends on SOC_SERIES_GD32F3X0
-
-	config SOC_GD32F350
-		bool "gd32f350"
-endchoice

soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.series

@@ -1,11 +0,0 @@
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_GD32F403
-
-source "soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403"
-
-config SOC_SERIES
-	default "gd32f403"
-
-endif   # SOC_SERIES_GD32F403

soc/arm/gd_gd32/gd32f403/Kconfig.soc

@@ -1,11 +0,0 @@
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32F403 MCU Selection"
-	depends on SOC_SERIES_GD32F403
-
-	config SOC_GD32F403
-		bool "gd32f403"
-
-endchoice

soc/arm/gd_gd32/gd32f4xx/Kconfig.soc

@@ -1,21 +0,0 @@
-# Copyright (c) 2021, Teslabs Engineering S.L.
-# Copyright (c) 2022, Rtone.
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32F4XX MCU Selection"
-	depends on SOC_SERIES_GD32F4XX
-
-	config SOC_GD32F405
-		bool "gd32f405"
-
-	config SOC_GD32F407
-		bool "gd32f407"
-
-	config SOC_GD32F450
-		bool "gd32f450"
-
-	config SOC_GD32F470
-		bool "gd32f470"
-
-endchoice

soc/arm/gd_gd32/gd32l23x/Kconfig.soc

@@ -1,10 +0,0 @@
-# Copyright (c) 2022 BrainCo Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32L23X MCU Selection"
-	depends on SOC_SERIES_GD32L23X
-
-	config SOC_GD32L233
-		bool "gd32l233"
-endchoice

soc/v2/gd_gd32/Kconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_GD_GD32
+	select HAS_GD32_HAL
+	select BUILD_OUTPUT_HEX
+	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+
+rsource "*/Kconfig"

soc/v2/gd_gd32/Kconfig.defconfig

@@ -1,9 +1,9 @@
 # Copyright (c) 2021, ATL Electronics
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_FAMILY_GD32
+if SOC_FAMILY_GD_GD32
 
-source "soc/arm/gd_gd32/*/Kconfig.defconfig.series"
+rsource "*/Kconfig.defconfig.series"
 
 config PINCTRL
 	default y
@@ -14,4 +14,4 @@ config RESET
 config CLOCK_CONTROL
 	default y
 
-endif # SOC_FAMILY_GD32
+endif # SOC_FAMILY_GD_GD32

soc/v2/gd_gd32/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_GD_GD32
+	bool
+
+config SOC_FAMILY
+	default "gd_gd32" if SOC_FAMILY_GD_GD32
+
+rsource "*/Kconfig.soc"

soc/v2/gd_gd32/gd32a50x/Kconfig

@@ -2,15 +2,12 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32A50X
-	bool "GigaDevice GD32A50X series Cortex-M33 MCU"
 	select ARM
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select ARMV8_M_DSP
 	select CPU_CORTEX_M33
-	select SOC_FAMILY_GD32_ARM
+	select SOC_FAMILY_GD_GD32
 	select GD32_HAS_AF_PINMUX
 	select GD32_HAS_IRC_40K
 	select PLATFORM_SPECIFIC_INIT
-	help
-	  Enable support for GigaDevice GD32A50X MCU series

soc/v2/gd_gd32/gd32a50x/Kconfig.defconfig.gd32a503

@@ -1,11 +1,12 @@
 # Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC
-	default "gd32a503"
+if SOC_GD32A503
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 
 config NUM_IRQS
 	default 82
+
+endif # SOC_GD32A503

soc/v2/gd_gd32/gd32a50x/Kconfig.defconfig.series

@@ -3,9 +3,9 @@
 
 if SOC_SERIES_GD32A50X
 
-source "soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32*"
-
 config SOC_SERIES
 	default "gd32a50x"
 
+rsource "Kconfig.defconfig.gd32*"
+
 endif # SOC_SERIES_GD32A50X

soc/v2/gd_gd32/gd32a50x/Kconfig.soc

@@ -0,0 +1,17 @@
+# Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32A50X
+	bool
+	help
+	  Enable support for GigaDevice GD32A50X MCU series
+
+config SOC_SERIES
+	default "gd32a50x" if SOC_SERIES_GD32A50X
+
+config SOC_GD32A503
+	bool
+	select SOC_SERIES_GD32A50X
+
+config SOC
+	default "gd32a503" if SOC_GD32A503

soc/v2/gd_gd32/gd32e10x/Kconfig

@@ -2,14 +2,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32E10X
-	bool "GigaDevice GD32E10X series Cortex-M4F MCU"
 	select ARM
 	select CPU_HAS_FPU
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select SOC_FAMILY_GD32_ARM
+	select SOC_FAMILY_GD_GD32
 	select GD32_HAS_AFIO_PINMUX
 	select GD32_HAS_IRC_40K
-	help
-	  Enable support for GigaDevice GD32E10X MCU series

soc/v2/gd_gd32/gd32e10x/Kconfig.defconfig.gd32e103

@@ -1,11 +1,12 @@
 # Copyright (c) 2021 YuLong Yao <feilongphone@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC
-	default "gd32e103"
+if SOC_GD32E103
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 
 config NUM_IRQS
 	default 83
+
+endif # SOC_GD32E103

soc/v2/gd_gd32/gd32e10x/Kconfig.defconfig.series

@@ -3,9 +3,9 @@
 
 if SOC_SERIES_GD32E10X
 
-source "soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32*"
-
 config SOC_SERIES
 	default "gd32e10x"
 
+rsource "Kconfig.defconfig.gd32*"
+
 endif # SOC_SERIES_GD32E10X

soc/v2/gd_gd32/gd32e10x/Kconfig.soc

@@ -0,0 +1,17 @@
+# Copyright (c) 2021 YuLong Yao <feilongphone@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32E10X
+	bool
+	help
+	  Enable support for GigaDevice GD32E10X MCU series
+
+config SOC_SERIES
+	default "gd32e10x" if SOC_SERIES_GD32E10X
+
+config SOC_GD32E103
+	bool
+	select SOC_SERIES_GD32E10X
+
+config SOC
+	default "gd32e103" if SOC_GD32E103

soc/v2/gd_gd32/gd32e50x/Kconfig

@@ -2,14 +2,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32E50X
-	bool "GigaDevice GD32E50X series Cortex-M33 MCU"
 	select ARM
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select CPU_CORTEX_M33
 	select ARMV8_M_DSP
-	select SOC_FAMILY_GD32_ARM
+	select SOC_FAMILY_GD_GD32
 	select GD32_HAS_AFIO_PINMUX
 	select GD32_HAS_IRC_40K
-	help
-	  Enable support for GigaDevice GD32E50X MCU series

soc/v2/gd_gd32/gd32e50x/Kconfig.defconfig.gd32e507

@@ -3,9 +3,6 @@
 
 if SOC_GD32E507
 
-config SOC
-	default "gd32e507"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 

soc/v2/gd_gd32/gd32e50x/Kconfig.defconfig.series

@@ -3,9 +3,9 @@
 
 if SOC_SERIES_GD32E50X
 
-source "soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32*"
-
 config SOC_SERIES
 	default "gd32e50x"
 
+rsource "Kconfig.defconfig.gd32*"
+
 endif # SOC_SERIES_GD32E50X

soc/v2/gd_gd32/gd32e50x/Kconfig.soc

@@ -0,0 +1,17 @@
+# Copyright (c) 2022, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32E50X
+	bool
+	help
+	  Enable support for GigaDevice GD32E50X MCU series
+
+config SOC_SERIES
+	default "gd32e50x" if SOC_SERIES_GD32E50X
+
+config SOC_GD32E507
+	bool
+	select SOC_SERIES_GD32E50X
+
+config SOC
+	default "gd32e507" if SOC_GD32E507

soc/v2/gd_gd32/gd32f3x0/Kconfig

@@ -2,12 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32F3X0
-	bool "GigaDevice GD32F3X0 series Cortex-M4F MCU"
 	select ARM
 	select CPU_HAS_FPU
 	select CPU_CORTEX_M4
-	select SOC_FAMILY_GD32_ARM
+	select SOC_FAMILY_GD_GD32
 	select GD32_HAS_AF_PINMUX
 	select GD32_HAS_IRC_40K
-	help
-	  Enable support for GigaDevice GD32F3X0 MCU series

soc/v2/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32f350

@@ -1,11 +1,12 @@
 # Copyright (c) 2021 BrainCo Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC
-	default "gd32f350"
+if SOC_GD32F350
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 
 config NUM_IRQS
 	default 68
+
+endif # SOC_GD32F350

soc/v2/gd_gd32/gd32f3x0/Kconfig.defconfig.series

@@ -3,9 +3,9 @@
 
 if SOC_SERIES_GD32F3X0
 
-source "soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32*"
-
 config SOC_SERIES
 	default "gd32f3x0"
 
+rsource "Kconfig.defconfig.gd32*"
+
 endif # SOC_SERIES_GD32F3X0

soc/v2/gd_gd32/gd32f3x0/Kconfig.soc

@@ -0,0 +1,17 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32F3X0
+	bool
+	help
+	  Enable support for GigaDevice GD32F3X0 MCU series
+
+config SOC_SERIES
+	default "gd32f3x0" if SOC_SERIES_GD32F3X0
+
+config SOC_GD32F350
+	bool
+	select SOC_SERIES_GD32F3X0
+
+config SOC
+	default "gd32f350" if SOC_GD32F350

soc/v2/gd_gd32/gd32f403/Kconfig

@@ -2,15 +2,12 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32F403
-	bool "GigaDevice GD32F403 series Cortex-M4F MCU"
 	select ARM
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select SOC_FAMILY_GD32_ARM
+	select SOC_FAMILY_GD_GD32
 	select GD32_HAS_AFIO_PINMUX
 	select GD32_HAS_IRC_40K
-	help
-	  Enable support for GigaDevice GD32F403 MCU series

soc/v2/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403

@@ -1,11 +1,12 @@
 # Copyright (c) 2021, ATL Electronics
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC
-	default "gd32f403"
+if SOC_GD32F403
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 
 config NUM_IRQS
 	default 68
+
+endif # SOC_GD32F403

soc/v2/gd_gd32/gd32f403/Kconfig.defconfig.series

@@ -0,0 +1,8 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32F403
+
+rsource "Kconfig.defconfig.gd32*"
+
+endif # SOC_SERIES_GD32F403

soc/v2/gd_gd32/gd32f403/Kconfig.soc

@@ -0,0 +1,17 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32F403
+	bool
+	help
+	  Enable support for GigaDevice GD32F403 MCU series
+
+config SOC_SERIES
+	default "gd32f403" if SOC_SERIES_GD32F403
+
+config SOC_GD32F403
+	bool
+	select SOC_SERIES_GD32F403
+
+config SOC
+	default "gd32f403" if SOC_GD32F403

soc/v2/gd_gd32/gd32f4xx/Kconfig

@@ -2,13 +2,10 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32F4XX
-	bool "GigaDevice GD32F4XX series Cortex-M4F MCU"
 	select ARM
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select CPU_CORTEX_M4
-	select SOC_FAMILY_GD32_ARM
+	select SOC_FAMILY_GD_GD32
 	select GD32_HAS_AF_PINMUX
 	select GD32_HAS_IRC_32K
-	help
-	  Enable support for GigaDevice GD32F4XX MCU series

soc/v2/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f405

@@ -3,9 +3,6 @@
 
 if SOC_GD32F405
 
-config SOC
-	default "gd32f405"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 

soc/v2/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f407

@@ -3,9 +3,6 @@
 
 if SOC_GD32F407
 
-config SOC
-	default "gd32f407"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 

soc/v2/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f450

@@ -3,9 +3,6 @@
 
 if SOC_GD32F450
 
-config SOC
-	default "gd32f450"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 

soc/v2/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f470

@@ -3,9 +3,6 @@
 
 if SOC_GD32F470
 
-config SOC
-	default "gd32f470"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 

soc/v2/gd_gd32/gd32f4xx/Kconfig.defconfig.series

@@ -3,9 +3,9 @@
 
 if SOC_SERIES_GD32F4XX
 
-source "soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32*"
-
 config SOC_SERIES
 	default "gd32f4xx"
 
+rsource "Kconfig.defconfig.gd32*"
+
 endif # SOC_SERIES_GD32F4XX

soc/v2/gd_gd32/gd32f4xx/Kconfig.soc

@@ -0,0 +1,33 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# Copyright (c) 2022, Rtone.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32F4XX
+	bool
+	help
+	  Enable support for GigaDevice GD32F4XX MCU series
+
+config SOC_SERIES
+	default "gd32f4xx" if SOC_SERIES_GD32F4XX
+
+config SOC_GD32F405
+	bool
+	select SOC_SERIES_GD32F4XX
+
+config SOC_GD32F407
+	bool
+	select SOC_SERIES_GD32F4XX
+
+config SOC_GD32F450
+	bool
+	select SOC_SERIES_GD32F4XX
+
+config SOC_GD32F470
+	bool
+	select SOC_SERIES_GD32F4XX
+
+config SOC
+	default "gd32f405" if SOC_GD32F405
+	default "gd32f407" if SOC_GD32F407
+	default "gd32f450" if SOC_GD32F450
+	default "gd32f470" if SOC_GD32F470

soc/v2/gd_gd32/gd32l23x/Kconfig

@@ -2,13 +2,10 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32L23X
-	bool "GigaDevice GD32L23X series Cortex-M23 MCU"
 	select ARM
 	select CPU_CORTEX_M23
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select SOC_FAMILY_GD32_ARM
+	select SOC_FAMILY_GD_GD32
 	select GD32_HAS_AF_PINMUX
 	select GD32_HAS_IRC_32K
-	help
-	  Enable support for GigaDevice GD32L23X MCU series

soc/v2/gd_gd32/gd32l23x/Kconfig.defconfig.gd32l233

@@ -1,11 +1,12 @@
 # Copyright (c) 2022 BrainCo Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC
-	default "gd32l233"
+if SOC_GD32L233
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 
 config NUM_IRQS
 	default 69
+
+endif # SOC_GD32L233

soc/v2/gd_gd32/gd32l23x/Kconfig.defconfig.series

@@ -3,9 +3,9 @@
 
 if SOC_SERIES_GD32L23X
 
-source "soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32*"
-
 config SOC_SERIES
 	default "gd32l23x"
 
+rsource "Kconfig.defconfig.gd32*"
+
 endif # SOC_SERIES_GD32L23X

soc/v2/gd_gd32/gd32l23x/Kconfig.soc

@@ -0,0 +1,17 @@
+# Copyright (c) 2022 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32L23X
+	bool
+	help
+	  Enable support for GigaDevice GD32L23X MCU series
+
+config SOC_SERIES
+	default "gd32l23x" if SOC_SERIES_GD32L23X
+
+config SOC_GD32L233
+	bool
+	select SOC_SERIES_GD32L23X
+
+config SOC
+	default "gd32l233" if SOC_GD32L233

soc/v2/gd_gd32/soc.yml

@@ -0,0 +1,27 @@
+family:
+- name: gd_gd32
+  series:
+  - name: gd32a50x
+    socs:
+    - name: gd32a503
+  - name: gd32e10x
+    socs:
+    - name: gd32e103
+  - name: gd32e50x
+    socs:
+    - name: gd32e507
+  - name: gd32f3x0
+    socs:
+    - name: gd32f350
+  - name: gd32f4xx
+    socs:
+    - name: gd32f405
+    - name: gd32f407
+    - name: gd32f450
+    - name: gd32f470
+  - name: gd32f403
+    socs:
+    - name: gd32f403
+  - name: gd32l23x
+    socs:
+    - name: gd32l233

tests/drivers/watchdog/wdt_basic_api/testcase.yaml

@@ -9,7 +9,7 @@ tests:
       not (CONFIG_WDT_SAM or dt_compat_enabled("st,stm32-window-watchdog")
        or dt_compat_enabled("st,stm32-watchdog") or CONFIG_SOC_FAMILY_LPC or
        CONFIG_SOC_SERIES_IMX_RT6XX or CONFIG_SOC_SERIES_IMX_RT5XX or
-       CONFIG_SOC_FAMILY_GD32 or SOC_SERIES_GD32VF103)
+       CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103)
     platform_exclude:
       - mec15xxevb_assy6853
       - s32z270dc2_rtu0_r52