boards: xtensa: intel_adsp_cavs25_tgph: change to board variant

Change `intel_adsp_cavs25_tgph` board definition to be HWMv2 board
variant `intel_adsp_cavs25/intel_tgl_adsp/tgph`

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>

boards/intel/intel_adsp_cavs25/Kconfig.intel_adsp_cavs25_tgph

@@ -1,5 +0,0 @@
-# Copyright (c) 2024 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_INTEL_ADSP_CAVS25_TGPH
-	select SOC_INTEL_CAVS_V25

boards/intel/intel_adsp_cavs25/board.cmake

@@ -13,7 +13,7 @@ if(CONFIG_BOARD_INTEL_ADSP_CAVS25)
 board_set_rimage_target(tgl)
 endif()
 
-if(CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH)
+if(CONFIG_BOARD_INTEL_ADSP_CAVS25_INTEL_TGL_ADSP_TGPH)
 board_set_rimage_target(tgl-h)
 endif()
 

boards/intel/intel_adsp_cavs25/board.yml

@@ -1,11 +1,7 @@
-boards:
-
-  - name: intel_adsp_cavs25
-    vendor: intel
-    socs:
-      - name: intel_tgl_adsp
-
-  - name: intel_adsp_cavs25_tgph
-    vendor: intel
-    socs:
-      - name: intel_tgl_adsp
+board:
+  name: intel_adsp_cavs25
+  vendor: intel
+  socs:
+    - name: intel_tgl_adsp
+      variants:
+        - name: 'tgph'

boards/intel/intel_adsp_cavs25/intel_adsp_cavs25_defconfig

@@ -1,3 +1,5 @@
+# Copyright (c) 2020-2024 Intel Corporation
+#
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_MAIN_STACK_SIZE=2048

boards/intel/intel_adsp_cavs25/intel_adsp_cavs25_intel_tgl_adsp_tgph.yaml

@@ -1,4 +1,4 @@
-identifier: intel_adsp_cavs25_tgph
+identifier: intel_adsp_cavs25/intel_tgl_adsp/tgph
 name: cAVS 2.5 Audio DSP for Tiger Lake H PCH (Converged Audio Voice and Speech)
 type: mcu
 arch: xtensa

boards/intel/intel_adsp_cavs25/intel_adsp_cavs25_intel_tgl_adsp_tgph_defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2020-2024 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
+
+CONFIG_MP_MAX_NUM_CPUS=2
+CONFIG_CORE_COUNT=2

boards/intel/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig

@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_MAIN_STACK_SIZE=2048
-
-CONFIG_GEN_ISR_TABLES=y
-CONFIG_GEN_IRQ_VECTOR_TABLE=n
-
-CONFIG_XTENSA_RESET_VECTOR=y
-
-CONFIG_XTENSA_USE_CORE_CRT1=y
-
-CONFIG_MULTI_LEVEL_INTERRUPTS=y
-CONFIG_2ND_LEVEL_INTERRUPTS=y
-
-CONFIG_BUILD_OUTPUT_BIN=n
-
-CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
-
-CONFIG_DCACHE_LINE_SIZE=64