soc: board: intel_socfpga_std: Align names to 'Cyclone V'
Align all names to `cyclonev` instead of using `cyclone5`. Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
This commit is contained in:
committed by
Carles Cufi
parent
402366117a
commit
8dc2b911f6
@@ -2,6 +2,6 @@
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CYCLONEV_SOCDK
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select SOC_CYCLONE5
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select SOC_CYCLONEV
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help
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Intel Cyclone V Development Kit
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@@ -6,12 +6,12 @@
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* this file is based on the GSRD DTS for Linux
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*/
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#include "intel_socfpga_std/socfpga_cyclone5.dtsi"
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#include "intel_socfpga_std/socfpga_cyclonev.dtsi"
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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model = "Altera SOCFPGA Cyclone V SoC Development Kit";
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compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
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compatible = "altr,socfpga-cyclonev-socdk", "altr,socfpga-cyclonev", "altr,socfpga";
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ddr0: memory@0 {
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name = "memory";
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@@ -1,7 +1,7 @@
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# Copyright (c) 2022-2024 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_CYCLONE5
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config SOC_SERIES_CYCLONEV
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select ARM
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select CPU_CORTEX_A9
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select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
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@@ -1,7 +1,7 @@
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# Copyright (c) 2022-2024 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_CYCLONE5
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if SOC_CYCLONEV
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config NUM_IRQS
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int
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@@ -1,8 +1,8 @@
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# Copyright (c) 2022-2024 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_CYCLONE5
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if SOC_SERIES_CYCLONEV
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rsource "Kconfig.defconfig.cyclonev*"
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endif # SOC_SERIES_CYCLONE5
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endif # SOC_SERIES_CYCLONEV
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@@ -1,20 +1,20 @@
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# Copyright (c) 2021-2024 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_CYCLONE5
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config SOC_SERIES_CYCLONEV
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bool
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select SOC_FAMILY_INTEL_SOCFPGA_STD
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help
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Intel SoC FPGA Cyclone V Series
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config SOC_SERIES
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default "cyclonev" if SOC_SERIES_CYCLONE5
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default "cyclonev" if SOC_SERIES_CYCLONEV
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config SOC_CYCLONE5
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config SOC_CYCLONEV
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bool
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select SOC_SERIES_CYCLONE5
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select SOC_SERIES_CYCLONEV
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help
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Intel SoC FPGA Cyclone V
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config SOC
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default "intel_socfpga_std_cyclonev" if SOC_CYCLONE5
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default "intel_socfpga_std_cyclonev" if SOC_CYCLONEV
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