include/dt-bindings/clock: stm32: Add clock sources bindings
Add clock sources bindings on F0/F3/G0/G4/L0/L1/L4/WB/WL series. Due to inconsistencies, some common bindings are now split: F1 -> F0/F1/F3 L4 -> L4/G4/WB Update .dtsi files when required In a first step, allowed sources are limited to already supported clocks: LSI/LSE/HSI/HSE/MSI/PCLK/PLLCLK/SYSCLK Support for other clocks such as HSI48, SAIXCLK, ... is left for a next step. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
committed by
Carles Cufí
Carles Cufí
parent
e579027d20
commit
988fe8d5a2
@@ -6,7 +6,7 @@
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*/
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#include <arm/armv6-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
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#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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@@ -6,7 +6,7 @@
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
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#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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@@ -7,7 +7,7 @@
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
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#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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@@ -51,9 +51,8 @@
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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driving-capability = <0>;
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status = "disabled";
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};
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@@ -354,7 +353,7 @@
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};
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can {
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compatible = "bosch,m_can-base";
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compatible = "bosch,m-can-base";
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#address-cells = <1>;
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#size-cells = <1>;
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std-filter-elements = <28>;
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@@ -6,7 +6,7 @@
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
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#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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@@ -11,25 +11,29 @@
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#include <zephyr/drivers/clock_control.h>
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X)
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#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32F3X)
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#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X)
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#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32G4X)
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#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32L0X)
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#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32L1X)
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#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32L5X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32L5X)
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#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32WBX)
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#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32WLX)
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#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32H7X)
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75
include/zephyr/dt-bindings/clock/stm32f0_clock.h
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75
include/zephyr/dt-bindings/clock/stm32f0_clock.h
Normal file
@@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
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/** Bus gatting clocks */
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#define STM32_CLOCK_BUS_AHB1 0x014
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#define STM32_CLOCK_BUS_APB2 0x018
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#define STM32_CLOCK_BUS_APB1 0x01c
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
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/** Peripheral clock sources */
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/** Fixed clocks */
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#define STM32_SRC_HSI 0x001
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#define STM32_SRC_LSE 0x002
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/* #define STM32_SRC_HSI48 0x003 */
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/** System clock */
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#define STM32_SRC_SYSCLK 0x004
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/** Bus clock */
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#define STM32_SRC_PCLK 0x005
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/** PLL clock */
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#define STM32_SRC_PLLCLK 0x006
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#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
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#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
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/**
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* @brief STM32 clock configuration bit field.
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*
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* - reg (1/2/3) [ 0 : 7 ]
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* - shift (0..31) [ 8 : 12 ]
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* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
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* - val (0..7) [ 16 : 18 ]
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*
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* @param reg RCC_CFGRx register offset
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* @param shift Position within RCC_CFGRx.
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* @param mask Mask for the RCC_CFGRx field.
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* @param val Clock value (0, 1, ... 7).
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*/
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#define STM32_CLOCK_REG_MASK 0xFFU
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#define STM32_CLOCK_REG_SHIFT 0U
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#define STM32_CLOCK_SHIFT_MASK 0x1FU
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#define STM32_CLOCK_SHIFT_SHIFT 8U
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#define STM32_CLOCK_MASK_MASK 0x7U
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#define STM32_CLOCK_MASK_SHIFT 13U
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#define STM32_CLOCK_VAL_MASK 0x7U
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#define STM32_CLOCK_VAL_SHIFT 16U
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#define STM32_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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/** @brief RCC_CFGRx register offset */
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#define CFGR3_REG 0x30
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/** @brief Device clk sources selection helpers */
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/** CFGR3 devices */
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#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
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#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
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#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG)
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#define USB_SEL(val) STM32_CLOCK(val, 1, 7, CFGR3_REG)
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#define ADC_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG)
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#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG)
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#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */
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85
include/zephyr/dt-bindings/clock/stm32f3_clock.h
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85
include/zephyr/dt-bindings/clock/stm32f3_clock.h
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@@ -0,0 +1,85 @@
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
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/** Bus gatting clocks */
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#define STM32_CLOCK_BUS_AHB1 0x014
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#define STM32_CLOCK_BUS_APB2 0x018
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#define STM32_CLOCK_BUS_APB1 0x01c
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
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/** Peripheral clock sources */
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/* RM0316, §9.4.13 Clock configuration register (RCC_CFGR3) */
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/** Fixed clocks */
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#define STM32_SRC_HSI 0x001
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#define STM32_SRC_LSE 0x002
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/* #define STM32_SRC_HSI48 0x003 */
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/** System clock */
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#define STM32_SRC_SYSCLK 0x004
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/** Bus clock */
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#define STM32_SRC_PCLK 0x005
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/** PLL clock */
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#define STM32_SRC_PLLCLK 0x006
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#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
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#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
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/**
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* @brief STM32 clock configuration bit field.
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*
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* - reg (1/2/3) [ 0 : 7 ]
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* - shift (0..31) [ 8 : 12 ]
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* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
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* - val (0..7) [ 16 : 18 ]
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*
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* @param reg RCC_CFGRx register offset
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* @param shift Position within RCC_CFGRx.
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* @param mask Mask for the RCC_CFGRx field.
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* @param val Clock value (0, 1, ... 7).
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*/
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#define STM32_CLOCK_REG_MASK 0xFFU
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#define STM32_CLOCK_REG_SHIFT 0U
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#define STM32_CLOCK_SHIFT_MASK 0x1FU
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#define STM32_CLOCK_SHIFT_SHIFT 8U
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#define STM32_CLOCK_MASK_MASK 0x7U
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#define STM32_CLOCK_MASK_SHIFT 13U
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#define STM32_CLOCK_VAL_MASK 0x7U
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#define STM32_CLOCK_VAL_SHIFT 16U
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#define STM32_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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/** @brief RCC_CFGRx register offset */
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#define CFGR3_REG 0x30
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/** @brief Device clk sources selection helpers) */
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/** CFGR3 devices */
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#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
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#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
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#define I2C2_SEL(val) STM32_CLOCK(val, 1, 5, CFGR3_REG)
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#define I2C3_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG)
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#define TIM1_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG)
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#define TIM8_SEL(val) STM32_CLOCK(val, 1, 9, CFGR3_REG)
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#define TIM15_SEL(val) STM32_CLOCK(val, 1, 10, CFGR3_REG)
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#define TIM16_SEL(val) STM32_CLOCK(val, 1, 11, CFGR3_REG)
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#define TIM17_SEL(val) STM32_CLOCK(val, 1, 13, CFGR3_REG)
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#define TIM20_SEL(val) STM32_CLOCK(val, 1, 15, CFGR3_REG)
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#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG)
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#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG)
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#define USART4_SEL(val) STM32_CLOCK(val, 3, 20, CFGR3_REG)
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#define USART5_SEL(val) STM32_CLOCK(val, 3, 22, CFGR3_REG)
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#define TIM2_SEL(val) STM32_CLOCK(val, 1, 24, CFGR3_REG)
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#define TIM3_4_SEL(val) STM32_CLOCK(val, 1, 25, CFGR3_REG)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */
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@@ -6,8 +6,6 @@
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
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/** Peripheral clock sources */
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/** Bus clocks */
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#define STM32_CLOCK_BUS_IOP 0x034
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#define STM32_CLOCK_BUS_AHB1 0x038
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@@ -17,4 +15,80 @@
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
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/** Peripheral clock sources */
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/* RM0444, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */
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/** Fixed clocks */
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#define STM32_SRC_HSI 0x001
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#define STM32_SRC_MSI 0x002
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#define STM32_SRC_LSE 0x003
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#define STM32_SRC_LSI 0x004
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/** System clock */
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#define STM32_SRC_SYSCLK 0x005
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/** Peripheral bus clock */
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#define STM32_SRC_PCLK 0x006
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/** PLL clock */
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#define STM32_SRC_PLLCLK 0x007
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#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
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#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
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/**
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* @brief STM32 clock configuration bit field.
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*
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* - reg (1/2/3) [ 0 : 7 ]
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* - shift (0..31) [ 8 : 12 ]
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* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
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* - val (0..7) [ 16 : 18 ]
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*
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* @param reg RCC_CCIPRx register offset
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* @param shift Position within RCC_CCIPRx.
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* @param mask Mask for the RCC_CCIPRx field.
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* @param val Clock value (0, 1, ... 7).
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*/
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#define STM32_CLOCK_REG_MASK 0xFFU
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#define STM32_CLOCK_REG_SHIFT 0U
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#define STM32_CLOCK_SHIFT_MASK 0x1FU
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#define STM32_CLOCK_SHIFT_SHIFT 8U
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#define STM32_CLOCK_MASK_MASK 0x7U
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#define STM32_CLOCK_MASK_SHIFT 13U
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#define STM32_CLOCK_VAL_MASK 0x7U
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#define STM32_CLOCK_VAL_SHIFT 16U
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#define STM32_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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/** @brief RCC_CCIPR register offset */
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#define CCIPR_REG 0x54
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#define CCIPR2_REG 0x58
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/** @brief Device clk sources selection helpers */
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/** CCIPR devices */
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#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
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#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
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#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
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#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG)
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#define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
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#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
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#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
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#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
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#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
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#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
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#define TIM1_SEL(val) STM32_CLOCK(val, 1, 22, CCIPR_REG)
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#define TIM15_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG)
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#define RNG_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
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#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
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/** CCIPR2 devices */
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#define I2S1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG)
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#define I2S2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR2_REG)
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#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR2_REG)
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#define USB_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */
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95
include/zephyr/dt-bindings/clock/stm32g4_clock.h
Normal file
95
include/zephyr/dt-bindings/clock/stm32g4_clock.h
Normal file
@@ -0,0 +1,95 @@
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/*
|
||||
* Copyright (c) 2022 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
|
||||
|
||||
/** Bus clocks */
|
||||
#define STM32_CLOCK_BUS_AHB1 0x048
|
||||
#define STM32_CLOCK_BUS_AHB2 0x04c
|
||||
#define STM32_CLOCK_BUS_AHB3 0x050
|
||||
#define STM32_CLOCK_BUS_APB1 0x058
|
||||
#define STM32_CLOCK_BUS_APB1_2 0x05c
|
||||
#define STM32_CLOCK_BUS_APB2 0x060
|
||||
|
||||
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
|
||||
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
|
||||
|
||||
/** Peripheral clock sources */
|
||||
/* RM0440, § Clock configuration register (RCC_CCIPRx) */
|
||||
|
||||
/** Fixed clocks */
|
||||
#define STM32_SRC_HSI 0x001
|
||||
/* #define STM32_SRC_HSI48 0x002 */
|
||||
#define STM32_SRC_LSE 0x003
|
||||
#define STM32_SRC_LSI 0x004
|
||||
#define STM32_SRC_MSI 0x005
|
||||
/** System clock */
|
||||
#define STM32_SRC_SYSCLK 0x006
|
||||
/** Bus clock */
|
||||
#define STM32_SRC_PCLK 0x007
|
||||
/** PLL clocks */
|
||||
#define STM32_SRC_PLLCLK 0x008
|
||||
/* TODO: PLLSAI clocks */
|
||||
|
||||
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
|
||||
#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
|
||||
|
||||
/**
|
||||
* @brief STM32 clock configuration bit field.
|
||||
*
|
||||
* - reg (1/2/3) [ 0 : 7 ]
|
||||
* - shift (0..31) [ 8 : 12 ]
|
||||
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
|
||||
* - val (0..7) [ 16 : 18 ]
|
||||
*
|
||||
* @param reg RCC_CCIPRx register offset
|
||||
* @param shift Position within RCC_CCIPRx.
|
||||
* @param mask Mask for the RCC_CCIPRx field.
|
||||
* @param val Clock value (0, 1, ... 7).
|
||||
*/
|
||||
|
||||
#define STM32_CLOCK_REG_MASK 0xFFU
|
||||
#define STM32_CLOCK_REG_SHIFT 0U
|
||||
#define STM32_CLOCK_SHIFT_MASK 0x1FU
|
||||
#define STM32_CLOCK_SHIFT_SHIFT 8U
|
||||
#define STM32_CLOCK_MASK_MASK 0x7U
|
||||
#define STM32_CLOCK_MASK_SHIFT 13U
|
||||
#define STM32_CLOCK_VAL_MASK 0x7U
|
||||
#define STM32_CLOCK_VAL_SHIFT 16U
|
||||
|
||||
#define STM32_CLOCK(val, mask, shift, reg) \
|
||||
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
|
||||
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
|
||||
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
|
||||
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
|
||||
|
||||
/** @brief RCC_CCIPR register offset */
|
||||
#define CCIPR_REG 0x88
|
||||
#define CCIPR2_REG 0x9C
|
||||
|
||||
/** @brief Device clk sources selection helpers */
|
||||
/** CCIPR devices */
|
||||
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
|
||||
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
|
||||
#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
|
||||
#define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
|
||||
#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
|
||||
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
|
||||
#define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
|
||||
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
|
||||
#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
|
||||
#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
|
||||
#define LPTIM3_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
|
||||
#define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG)
|
||||
#define SAI2_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR_REG)
|
||||
#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
|
||||
#define ADC12_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG)
|
||||
#define ADC34_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
|
||||
/** CCIPR2 devices */
|
||||
#define I2C4_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG)
|
||||
#define QSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */
|
||||
@@ -6,9 +6,7 @@
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
|
||||
|
||||
/** Peripheral clock sources */
|
||||
|
||||
/** Bus clocks */
|
||||
/** Bus gatting clocks */
|
||||
#define STM32_CLOCK_BUS_IOP 0x02c
|
||||
#define STM32_CLOCK_BUS_AHB1 0x030
|
||||
#define STM32_CLOCK_BUS_APB2 0x034
|
||||
@@ -17,4 +15,62 @@
|
||||
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
|
||||
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
|
||||
|
||||
/** Peripheral clock sources */
|
||||
/* RM0367, §7.3.20 Clock configuration register (RCC_CCIPR) */
|
||||
|
||||
/** Fixed clocks */
|
||||
#define STM32_SRC_HSE 0x001
|
||||
#define STM32_SRC_LSE 0x002
|
||||
#define STM32_SRC_LSI 0x003
|
||||
#define STM32_SRC_HSI 0x004
|
||||
/** System clock */
|
||||
#define STM32_SRC_SYSCLK 0x005
|
||||
/** Bus clock */
|
||||
#define STM32_SRC_PCLK 0x006
|
||||
|
||||
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSE
|
||||
#define STM32_SRC_CLOCK_MAX STM32_SRC_PCLK
|
||||
|
||||
/**
|
||||
* @brief STM32 clock configuration bit field.
|
||||
*
|
||||
* - reg (1/2/3) [ 0 : 7 ]
|
||||
* - shift (0..31) [ 8 : 12 ]
|
||||
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
|
||||
* - val (0..7) [ 16 : 18 ]
|
||||
*
|
||||
* @param reg RCC_CCIPRx register offset
|
||||
* @param shift Position within RCC_CCIPRx.
|
||||
* @param mask Mask for the RCC_CCIPRx field.
|
||||
* @param val Clock value (0, 1, ... 7).
|
||||
*/
|
||||
|
||||
#define STM32_CLOCK_REG_MASK 0xFFU
|
||||
#define STM32_CLOCK_REG_SHIFT 0U
|
||||
#define STM32_CLOCK_SHIFT_MASK 0x1FU
|
||||
#define STM32_CLOCK_SHIFT_SHIFT 8U
|
||||
#define STM32_CLOCK_MASK_MASK 0x7U
|
||||
#define STM32_CLOCK_MASK_SHIFT 13U
|
||||
#define STM32_CLOCK_VAL_MASK 0x7U
|
||||
#define STM32_CLOCK_VAL_SHIFT 16U
|
||||
|
||||
#define STM32_CLOCK(val, mask, shift, reg) \
|
||||
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
|
||||
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
|
||||
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
|
||||
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
|
||||
|
||||
/** @brief RCC_CCIPR register offset */
|
||||
#define CCIPR_REG 0x4C
|
||||
|
||||
/** @brief Device clk sources selection helpers */
|
||||
/** CCIPR devices */
|
||||
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
|
||||
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
|
||||
#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
|
||||
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
|
||||
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
|
||||
#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
|
||||
#define HSI48_SEL(val) STM32_CLOCK(val, 1, 26, CCIPR_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */
|
||||
|
||||
@@ -6,9 +6,7 @@
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
|
||||
|
||||
/** Peripheral clock sources */
|
||||
|
||||
/** Bus clocks */
|
||||
/** Bus gatting clocks */
|
||||
#define STM32_CLOCK_BUS_AHB1 0x01c
|
||||
#define STM32_CLOCK_BUS_APB2 0x020
|
||||
#define STM32_CLOCK_BUS_APB1 0x024
|
||||
@@ -16,4 +14,49 @@
|
||||
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
|
||||
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */
|
||||
/** Peripheral clock sources */
|
||||
/* RM0038.pdf, §6.3.14 Control/status register (RCC_CSR) */
|
||||
|
||||
/** Fixed clocks */
|
||||
#define STM32_SRC_HSE 0x001
|
||||
#define STM32_SRC_LSE 0x002
|
||||
#define STM32_SRC_LSI 0x003
|
||||
|
||||
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSE
|
||||
#define STM32_SRC_CLOCK_MAX STM32_SRC_LSI
|
||||
|
||||
/**
|
||||
* @brief STM32 clock configuration bit field.
|
||||
*
|
||||
* - reg (1/2/3) [ 0 : 7 ]
|
||||
* - shift (0..31) [ 8 : 12 ]
|
||||
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
|
||||
* - val (0..7) [ 16 : 18 ]
|
||||
*
|
||||
* @param reg RCC_CCIPRx register offset
|
||||
* @param shift Position within RCC_CCIPRx.
|
||||
* @param mask Mask for the RCC_CCIPRx field.
|
||||
* @param val Clock value (0, 1, ... 7).
|
||||
*/
|
||||
|
||||
#define STM32_CLOCK_REG_MASK 0xFFU
|
||||
#define STM32_CLOCK_REG_SHIFT 0U
|
||||
#define STM32_CLOCK_SHIFT_MASK 0x1FU
|
||||
#define STM32_CLOCK_SHIFT_SHIFT 8U
|
||||
#define STM32_CLOCK_MASK_MASK 0x7U
|
||||
#define STM32_CLOCK_MASK_SHIFT 13U
|
||||
#define STM32_CLOCK_VAL_MASK 0x7U
|
||||
#define STM32_CLOCK_VAL_SHIFT 16U
|
||||
|
||||
#define STM32_CLOCK(val, mask, shift, reg) \
|
||||
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
|
||||
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
|
||||
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
|
||||
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
|
||||
|
||||
/** @brief RCC_CSR register offset */
|
||||
#define CSR_REG 0x34
|
||||
|
||||
#define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */
|
||||
|
||||
@@ -6,8 +6,6 @@
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_
|
||||
|
||||
/** Peripheral clock sources */
|
||||
|
||||
/** Bus clocks */
|
||||
#define STM32_CLOCK_BUS_AHB1 0x048
|
||||
#define STM32_CLOCK_BUS_AHB2 0x04c
|
||||
@@ -19,4 +17,86 @@
|
||||
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
|
||||
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
|
||||
|
||||
/** Peripheral clock sources */
|
||||
/* RM0351/RM0432/RM0438, § Clock configuration register (RCC_CCIPRx) */
|
||||
|
||||
/** Fixed clocks */
|
||||
#define STM32_SRC_HSI 0x001
|
||||
/* #define STM32_SRC_HSI48 0x002 */
|
||||
#define STM32_SRC_LSE 0x003
|
||||
#define STM32_SRC_LSI 0x004
|
||||
#define STM32_SRC_MSI 0x005
|
||||
/** System clock */
|
||||
#define STM32_SRC_SYSCLK 0x006
|
||||
/** Bus clock */
|
||||
#define STM32_SRC_PCLK 0x007
|
||||
/** PLL clocks */
|
||||
#define STM32_SRC_PLLCLK 0x008
|
||||
/* TODO: PLLSAI clocks */
|
||||
|
||||
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
|
||||
#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
|
||||
|
||||
/**
|
||||
* @brief STM32 clock configuration bit field.
|
||||
*
|
||||
* - reg (1/2/3) [ 0 : 7 ]
|
||||
* - shift (0..31) [ 8 : 12 ]
|
||||
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
|
||||
* - val (0..7) [ 16 : 18 ]
|
||||
*
|
||||
* @param reg RCC_CCIPRx register offset
|
||||
* @param shift Position within RCC_CCIPRx.
|
||||
* @param mask Mask for the RCC_CCIPRx field.
|
||||
* @param val Clock value (0, 1, ... 7).
|
||||
*/
|
||||
|
||||
#define STM32_CLOCK_REG_MASK 0xFFU
|
||||
#define STM32_CLOCK_REG_SHIFT 0U
|
||||
#define STM32_CLOCK_SHIFT_MASK 0x1FU
|
||||
#define STM32_CLOCK_SHIFT_SHIFT 8U
|
||||
#define STM32_CLOCK_MASK_MASK 0x7U
|
||||
#define STM32_CLOCK_MASK_SHIFT 13U
|
||||
#define STM32_CLOCK_VAL_MASK 0x7U
|
||||
#define STM32_CLOCK_VAL_SHIFT 16U
|
||||
|
||||
#define STM32_CLOCK(val, mask, shift, reg) \
|
||||
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
|
||||
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
|
||||
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
|
||||
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
|
||||
|
||||
/** @brief RCC_CCIPR register offset */
|
||||
#define CCIPR_REG 0x88
|
||||
#define CCIPR2_REG 0x9C
|
||||
|
||||
/** @brief Device clk sources selection helpers */
|
||||
/** CCIPR devices */
|
||||
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
|
||||
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
|
||||
#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
|
||||
#define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
|
||||
#define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
|
||||
#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
|
||||
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
|
||||
#define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
|
||||
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
|
||||
#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
|
||||
#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
|
||||
#define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG)
|
||||
#define SAI2_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR_REG)
|
||||
#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
|
||||
#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG)
|
||||
#define SWPMI1_SEL(val) STM32_CLOCK(val, 1, 30, CCIPR_REG)
|
||||
#define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 31, CCIPR_REG)
|
||||
/** CCIPR2 devices */
|
||||
#define I2C4_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG)
|
||||
#define DFSDM_SEL(val) STM32_CLOCK(val, 1, 2, CCIPR2_REG)
|
||||
#define ADFSDM_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR2_REG)
|
||||
/* #define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG) */
|
||||
/* #define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG) */
|
||||
#define DSI_SEL(val) STM32_CLOCK(val, 1, 12, CCIPR2_REG)
|
||||
#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG)
|
||||
#define OSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */
|
||||
|
||||
@@ -84,7 +84,7 @@
|
||||
#define CCIPR2_REG 0xE4
|
||||
#define CCIPR3_REG 0xE8
|
||||
|
||||
/** @brief Device clk sources selection helpers (RM0399.pdf) */
|
||||
/** @brief Device clk sources selection helpers */
|
||||
/** CCIPR1 devices */
|
||||
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG)
|
||||
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG)
|
||||
@@ -110,8 +110,6 @@
|
||||
#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG)
|
||||
#define OCTOSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG)
|
||||
/** CCIPR3 devices */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */
|
||||
#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG)
|
||||
#define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG)
|
||||
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG)
|
||||
@@ -120,3 +118,5 @@
|
||||
#define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG)
|
||||
#define DAC1_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR3_REG)
|
||||
#define ADF1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR3_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */
|
||||
|
||||
85
include/zephyr/dt-bindings/clock/stm32wb_clock.h
Normal file
85
include/zephyr/dt-bindings/clock/stm32wb_clock.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2022 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
|
||||
|
||||
/** Bus clocks */
|
||||
#define STM32_CLOCK_BUS_AHB1 0x048
|
||||
#define STM32_CLOCK_BUS_AHB2 0x04c
|
||||
#define STM32_CLOCK_BUS_AHB3 0x050
|
||||
#define STM32_CLOCK_BUS_APB1 0x058
|
||||
#define STM32_CLOCK_BUS_APB1_2 0x05c
|
||||
#define STM32_CLOCK_BUS_APB2 0x060
|
||||
|
||||
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
|
||||
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
|
||||
|
||||
/** Peripheral clock sources */
|
||||
/* RM0434, § Clock configuration register (RCC_CCIPRx) */
|
||||
|
||||
/** Fixed clocks */
|
||||
#define STM32_SRC_HSI 0x001
|
||||
/* #define STM32_SRC_HSI48 0x002 */
|
||||
#define STM32_SRC_LSE 0x003
|
||||
#define STM32_SRC_LSI 0x004
|
||||
#define STM32_SRC_MSI 0x005
|
||||
/** System clock */
|
||||
#define STM32_SRC_SYSCLK 0x006
|
||||
/** Bus clock */
|
||||
#define STM32_SRC_PCLK 0x007
|
||||
/** PLL clocks */
|
||||
#define STM32_SRC_PLLCLK 0x008
|
||||
/* TODO: PLLSAI clocks */
|
||||
|
||||
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
|
||||
#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
|
||||
|
||||
/**
|
||||
* @brief STM32 clock configuration bit field.
|
||||
*
|
||||
* - reg (1/2/3) [ 0 : 7 ]
|
||||
* - shift (0..31) [ 8 : 12 ]
|
||||
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
|
||||
* - val (0..7) [ 16 : 18 ]
|
||||
*
|
||||
* @param reg RCC_CCIPRx register offset
|
||||
* @param shift Position within RCC_CCIPRx.
|
||||
* @param mask Mask for the RCC_CCIPRx field.
|
||||
* @param val Clock value (0, 1, ... 7).
|
||||
*/
|
||||
|
||||
#define STM32_CLOCK_REG_MASK 0xFFU
|
||||
#define STM32_CLOCK_REG_SHIFT 0U
|
||||
#define STM32_CLOCK_SHIFT_MASK 0x1FU
|
||||
#define STM32_CLOCK_SHIFT_SHIFT 8U
|
||||
#define STM32_CLOCK_MASK_MASK 0x7U
|
||||
#define STM32_CLOCK_MASK_SHIFT 13U
|
||||
#define STM32_CLOCK_VAL_MASK 0x7U
|
||||
#define STM32_CLOCK_VAL_SHIFT 16U
|
||||
|
||||
#define STM32_CLOCK(val, mask, shift, reg) \
|
||||
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
|
||||
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
|
||||
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
|
||||
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
|
||||
|
||||
/** @brief RCC_CCIPR register offset */
|
||||
#define CCIPR_REG 0x88
|
||||
|
||||
/** @brief Device clk sources selection helpers */
|
||||
/** CCIPR devices */
|
||||
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
|
||||
#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
|
||||
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
|
||||
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
|
||||
#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
|
||||
#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
|
||||
#define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG)
|
||||
#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
|
||||
#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG)
|
||||
#define RNG_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */
|
||||
@@ -6,8 +6,6 @@
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
|
||||
|
||||
/** Peripheral clock sources */
|
||||
|
||||
/** Bus clocks */
|
||||
#define STM32_CLOCK_BUS_AHB1 0x048
|
||||
#define STM32_CLOCK_BUS_AHB2 0x04c
|
||||
@@ -20,4 +18,69 @@
|
||||
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
|
||||
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
|
||||
|
||||
/** Peripheral clock sources */
|
||||
/* RM0461, §6.4.29 Clock configuration register (RCC_CFGR3) */
|
||||
|
||||
/** Fixed clocks */
|
||||
#define STM32_SRC_HSI 0x001
|
||||
#define STM32_SRC_LSE 0x002
|
||||
#define STM32_SRC_LSI 0x003
|
||||
/* #define STM32_SRC_HSI48 0x004 */
|
||||
/** System clock */
|
||||
#define STM32_SRC_SYSCLK 0x005
|
||||
/** Bus clock */
|
||||
#define STM32_SRC_PCLK 0x006
|
||||
/** PLL clock */
|
||||
#define STM32_SRC_PLLCLK 0x007
|
||||
|
||||
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
|
||||
#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
|
||||
|
||||
/**
|
||||
* @brief STM32 clock configuration bit field.
|
||||
*
|
||||
* - reg (1/2/3) [ 0 : 7 ]
|
||||
* - shift (0..31) [ 8 : 12 ]
|
||||
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
|
||||
* - val (0..7) [ 16 : 18 ]
|
||||
*
|
||||
* @param reg RCC_CCIPRx register offset
|
||||
* @param shift Position within RCC_CCIPRx.
|
||||
* @param mask Mask for the RCC_CCIPRx field.
|
||||
* @param val Clock value (0, 1, ... 7).
|
||||
*/
|
||||
|
||||
#define STM32_CLOCK_REG_MASK 0xFFU
|
||||
#define STM32_CLOCK_REG_SHIFT 0U
|
||||
#define STM32_CLOCK_SHIFT_MASK 0x1FU
|
||||
#define STM32_CLOCK_SHIFT_SHIFT 8U
|
||||
#define STM32_CLOCK_MASK_MASK 0x7U
|
||||
#define STM32_CLOCK_MASK_SHIFT 13U
|
||||
#define STM32_CLOCK_VAL_MASK 0x7U
|
||||
#define STM32_CLOCK_VAL_SHIFT 16U
|
||||
|
||||
#define STM32_CLOCK(val, mask, shift, reg) \
|
||||
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
|
||||
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
|
||||
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
|
||||
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
|
||||
|
||||
/** @brief RCC_CCIPR register offset */
|
||||
#define CCIPR_REG 0x88
|
||||
|
||||
/** @brief Device clk sources selection helpers */
|
||||
/** CCIPR devices */
|
||||
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
|
||||
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
|
||||
#define SPI2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
|
||||
#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
|
||||
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
|
||||
#define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
|
||||
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
|
||||
#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
|
||||
#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
|
||||
#define LPTIM3_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG)
|
||||
#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG)
|
||||
#define RNG_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ */
|
||||
|
||||
Reference in New Issue
Block a user