soc: openisa_rv32m1: Port to HWMv2

Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

arch/common/CMakeLists.txt

@@ -71,7 +71,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
 
 # Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET.
 if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64
-    OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+    OR DEFINED CONFIG_SOC_OPENISA_RV32M1)
   # Exclamation mark is printable character with lowest number in ASCII table.
   # We are sure that this file will be included as a first.
   zephyr_linker_sources(ROM_START SORT_KEY ! rom_start_address.ld)

arch/riscv/core/fatal.c

@@ -163,7 +163,7 @@ void _Fault(z_arch_esf_t *esf)
 
 	__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
 
-#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
+#ifndef CONFIG_SOC_OPENISA_RV32M1
 	unsigned long mtval;
 	__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
 #endif
@@ -171,7 +171,7 @@ void _Fault(z_arch_esf_t *esf)
 	mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK;
 	LOG_ERR("");
 	LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
-#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
+#ifndef CONFIG_SOC_OPENISA_RV32M1
 	LOG_ERR("  mtval: %lx", mtval);
 #endif
 

modules/Kconfig.vega

@@ -3,7 +3,7 @@
 
 config VEGA_SDK_HAL
 	bool "RV32M1 VEGA SDK support"
-	depends on SOC_OPENISA_RV32M1_RISCV32
+	depends on SOC_OPENISA_RV32M1
 
 config HAS_RV32M1_LPUART
 	bool

soc/openisa/rv32m1/CMakeLists.txt

@@ -19,6 +19,8 @@ zephyr_sources(
   soc.c
 )
 
+zephyr_include_directories(.)
+
 zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
 
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/openisa/rv32m1/Kconfig

@@ -1,11 +1,8 @@
 # Copyright (c) 2018 Foundries.io Ltd
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_OPENISA_RV32M1_RISCV32
-	bool "OpenISA RV32M1 RISC-V cores"
+config SOC_OPENISA_RV32M1
 	select RISCV
-	# The following select is due to limitations in the linker script.
-	# (We can't make it a 'depends on' without causing a dependency loop).
 	select XIP
 	select HAS_RV32M1_LPUART
 	select HAS_RV32M1_LPI2C
@@ -23,7 +20,3 @@ config SOC_OPENISA_RV32M1_RISCV32
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
-	help
-	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
-	  this option to target the RI5CY or ZERO-RISCY core. This
-	  option should not be used to target either Arm core.

soc/openisa/rv32m1/Kconfig.defconfig

@@ -3,10 +3,7 @@
 # Copyright (c) 2018 Foundries.io Ltd
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_OPENISA_RV32M1_RISCV32
-
-config SOC
-	default "openisa_rv32m1"
+if SOC_OPENISA_RV32M1
 
 # 32 from event unit + 32 * (1 + max enabled INTMUX channel)
 config NUM_IRQS
@@ -122,4 +119,4 @@ config RV32M1_INTMUX_CHANNEL_7
 
 endif # MULTI_LEVEL_INTERRUPTS
 
-endif # SOC_OPENISA_RV32M1_RISCV32
+endif # SOC_OPENISA_RV32M1

soc/openisa/rv32m1/Kconfig.soc

@@ -0,0 +1,24 @@
+# Copyright (c) 2018 Foundries.io Ltd
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_OPENISA_RV32M1
+	bool
+	help
+	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
+	  this option to target the RI5CY or ZERO-RISCY core. This
+	  option should not be used to target either Arm core.
+
+config SOC_OPENISA_RV32M1_RI5CY
+	bool
+	select SOC_OPENISA_RV32M1
+	help
+	  OpenISA RV32M1 RI5CY core
+
+config SOC_OPENISA_RV32M1_ZERO_RISCY
+	bool
+	select SOC_OPENISA_RV32M1
+	help
+	  OpenISA RV32M1 ZERO-RISCY core
+
+config SOC
+	default "openisa_rv32m1" if SOC_OPENISA_RV32M1

soc/openisa/rv32m1/soc.yml

@@ -0,0 +1,5 @@
+socs:
+- name: openisa_rv32m1
+  cpuclusters:
+  - name: zero_riscy
+  - name: ri5cy

soc/soc_legacy/riscv/openisa_rv32m1/Kconfig

@@ -1,25 +0,0 @@
-# Copyright (c) 2018 Foundries.io Ltd
-# SPDX-License-Identifier: Apache-2.0
-
-# The OpenISA RV32M1 SoC directory in riscv supports the RISC-V
-# cores on OpenISA RV32M1 SoCs.
-#
-# The Zephyr "soc" abstraction isn't a great fit here. These SoCs (in
-# the strict physical sense of "systems on chip") also contain Arm
-# cores, so this type of "soc" doesn't really belong to a single "arch".
-#
-# However, due to constraints imposed by Zephyr's file hierarchy
-# conventions, those "other" cores would need to be supported under a
-# different soc subdirectory, e.g. soc/soc_legacy/arm instead of soc/soc_legacy/riscv.
-
-choice
-	prompt "OpenISA RV32M1 RISC-V Core Selection"
-	depends on SOC_OPENISA_RV32M1_RISCV32
-
-config SOC_OPENISA_RV32M1_RI5CY
-	bool "OpenISA RV32M1 RI5CY core"
-
-config SOC_OPENISA_RV32M1_ZERO_RISCY
-	bool "OpenISA RV32M1 ZERO-RISCY core"
-
-endchoice

subsys/bluetooth/controller/Kconfig

@@ -557,8 +557,8 @@ config BT_CTLR_FAL_SIZE
 	int "LE Controller-based Privacy White List size"
 	depends on BT_CTLR_FILTER_ACCEPT_LIST
 	default 8
-	range 1 8  if  (SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1_RISCV32)
-	range 1 16 if !(SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1_RISCV32)
+	range 1 8  if  (SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1)
+	range 1 16 if !(SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1)
 	help
 	  Set the size of the Filter Accept List for LE Controller-based Privacy.
 	  On nRF5x-based controllers, the hardware imposes a limit of 8 devices.
@@ -569,7 +569,7 @@ config BT_CTLR_RL_SIZE
 	depends on BT_CTLR_PRIVACY
 	default 8
 	range 1 8 if SOC_COMPATIBLE_NRF
-	range 1 8 if SOC_OPENISA_RV32M1_RISCV32
+	range 1 8 if SOC_OPENISA_RV32M1
 	help
 	  Set the size of the Resolving List for LE Controller-based Privacy.
 	  On nRF5x-based controllers, the hardware imposes a limit of 8 devices.

subsys/bluetooth/controller/Kconfig.ll_sw_split

@@ -63,7 +63,7 @@ config BT_LLL_VENDOR_NORDIC
 
 config BT_LLL_VENDOR_OPENISA
 	bool "Use OpenISA LLL"
-	depends on SOC_OPENISA_RV32M1_RISCV32
+	depends on SOC_OPENISA_RV32M1
 	select BT_CTLR_PHY_UPDATE_SUPPORT
 	select BT_CTLR_EXT_REJ_IND_SUPPORT
 	select BT_HAS_HCI_VS

subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c

@@ -542,11 +542,11 @@ void lll_conn_pdu_tx_prep(struct lll_conn *lll, struct pdu_data **pdu_data_tx)
 
 	p->rfu = 0U;
 
-#if !defined(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+#if !defined(CONFIG_SOC_OPENISA_RV32M1)
 #if !defined(CONFIG_BT_CTLR_DATA_LENGTH_CLEAR)
 	p->resv = 0U;
 #endif /* !CONFIG_BT_CTLR_DATA_LENGTH_CLEAR */
-#endif /* !CONFIG_SOC_OPENISA_RV32M1_RISCV32 */
+#endif /* !CONFIG_SOC_OPENISA_RV32M1 */
 
 	*pdu_data_tx = p;
 }

tests/bluetooth/ctrl_user_ext/CMakeLists.txt

@@ -13,7 +13,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF)
     ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic
     ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic
   )
-elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+elseif(CONFIG_SOC_OPENISA_RV32M1)
   zephyr_library_include_directories(
     ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa
     ${ZEPHYR_BASE}/bluetooth/hci/openisa

tests/bluetooth/df/connection_cte_req/CMakeLists.txt

@@ -27,7 +27,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF)
     ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic
     ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic
   )
-elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+elseif(CONFIG_SOC_OPENISA_RV32M1)
   zephyr_library_include_directories(
     ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa
     ${ZEPHYR_BASE}/bluetooth/hci/openisa

tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt

@@ -28,7 +28,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF)
     ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic
     ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic
   )
-elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+elseif(CONFIG_SOC_OPENISA_RV32M1)
   zephyr_library_include_directories(
     ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa
     ${ZEPHYR_BASE}/bluetooth/hci/openisa

tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt

@@ -26,7 +26,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF)
     ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic
     ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic
   )
-elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+elseif(CONFIG_SOC_OPENISA_RV32M1)
   zephyr_library_include_directories(
     ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa
     ${ZEPHYR_BASE}/bluetooth/hci/openisa

tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt

@@ -26,7 +26,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF)
     ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic
     ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic
   )
-elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+elseif(CONFIG_SOC_OPENISA_RV32M1)
   zephyr_library_include_directories(
     ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa
     ${ZEPHYR_BASE}/bluetooth/hci/openisa