boards: arm: bl5340_dvk: Convert to v2

Converts the board to hwmv2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

boards/boards_legacy/arm/bl5340_dvk/CMakeLists.txt

@@ -1,16 +0,0 @@
-# Copyright (c) 2019 Nordic Semiconductor ASA.
-# Copyright (c) 2021-2023 Laird Connectivity.
-# SPDX-License-Identifier: Apache-2.0
-
-if ((CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPP_NS)
-    AND CONFIG_BOARD_ENABLE_CPUNET)
-zephyr_library()
-zephyr_library_sources(bl5340_dvk_cpunet_reset.c)
-
-if (CONFIG_BUILD_WITH_TFM)
-  zephyr_library_include_directories(
-    $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/interface/include
-  )
-endif()
-
-endif()

boards/boards_legacy/arm/bl5340_dvk/Kconfig.board

@@ -1,18 +0,0 @@
-# BL5340-DVK board configuration
-
-# Copyright (c) 2021 Laird Connectivity
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_NRF5340_CPUAPP_QKAA
-
-config BOARD_BL5340_DVK_CPUAPP
-	bool "BL5340-DVK (nRF5340) Application MCU"
-
-config BOARD_BL5340_DVK_CPUAPP_NS
-	bool "BL5340-DVK (nRF5340) Application MCU non-secure"
-
-endif # SOC_NRF5340_CPUAPP_QKAA
-
-config BOARD_BL5340_DVK_CPUNET
-	bool "BL5340-DVK (nRF5340) Network MCU"
-	depends on SOC_NRF5340_CPUNET_QKAA

boards/laird_connect/bl5340_dvk/CMakeLists.txt

@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA.
+# Copyright (c) 2021-2023 Laird Connectivity.
+# SPDX-License-Identifier: Apache-2.0
+
+if((CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS)
+   AND CONFIG_BOARD_ENABLE_CPUNET)
+  zephyr_library()
+  zephyr_library_sources(bl5340_dvk_cpunet_reset.c)
+
+  if(CONFIG_BUILD_WITH_TFM)
+    zephyr_library_include_directories(
+      $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/interface/include
+    )
+  endif()
+endif()

boards/laird_connect/bl5340_dvk/Kconfig

@@ -4,7 +4,7 @@
 # Copyright (c) 2021-2023 Laird Connectivity
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
+if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
 
 config BOARD_ENABLE_DCDC_APP
 	bool "Application MCU DCDC converter"
@@ -39,7 +39,7 @@ config BOARD_ENABLE_CPUNET
 
 config DOMAIN_CPUNET_BOARD
 	string
-	default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
+	default "bl5340_dvk/nrf5340/cpunet"
 	depends on BOARD_ENABLE_CPUNET
 	help
 	  The board which will be used for CPUNET domain when creating a multi
@@ -47,16 +47,16 @@ config DOMAIN_CPUNET_BOARD
 	  another board. For example hci_ipc on the bl5340_dvk_cpunet for
 	  Bluetooth applications.
 
-endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
+endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
 
-if BOARD_BL5340_DVK_CPUNET
+if BOARD_BL5340_DVK_NRF5340_CPUNET
 
 config DOMAIN_CPUAPP_BOARD
 	string
-	default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUNET
+	default "bl5340_dvk/nrf5340/cpuapp"
 	help
 	  The board which will be used for CPUAPP domain when creating a multi
 	  image application where one or more images should be located on
 	  another board.
 
-endif # BOARD_BL5340_DVK_CPUNET
+endif # BOARD_BL5340_DVK_NRF5340_CPUNET

boards/laird_connect/bl5340_dvk/Kconfig.bl5340_dvk

@@ -0,0 +1,9 @@
+# BL5340-DVK board configuration
+
+# Copyright (c) 2021 Laird Connectivity
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BL5340_DVK
+	select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP
+	select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
+	select SOC_NRF5340_CPUNET_QKAA if BOARD_BL5340_DVK_NRF5340_CPUNET

boards/laird_connect/bl5340_dvk/Kconfig.defconfig

@@ -4,11 +4,7 @@
 # Copyright (c) 2021-2023 Laird Connectivity
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
-
-config BOARD
-	default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
-
+if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
 
 config I2C
 	default GPIO || DAC
@@ -41,7 +37,7 @@ config I2C
 DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
 DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
 
-if BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE
+if BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
 
 config FLASH_LOAD_SIZE
 	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
@@ -49,9 +45,9 @@ config FLASH_LOAD_SIZE
 config SRAM_SIZE
 	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)
 
-endif # BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE
+endif # BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
 
-if BOARD_BL5340_DVK_CPUAPP_NS
+if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
 
 config FLASH_LOAD_OFFSET
 	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
@@ -59,20 +55,7 @@ config FLASH_LOAD_OFFSET
 config FLASH_LOAD_SIZE
 	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
 
-endif # BOARD_BL5340_DVK_CPUAPP_NS
-
-endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
-
-config BOARD
-	default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUNET
-
-config IPM_NRFX
-	default IPM
-
-config MBOX_NRFX_IPC
-	default MBOX
-
-if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
+endif # BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
 
 choice BT_HCI_BUS_TYPE
 	default BT_HCI_IPC if BT
@@ -93,7 +76,6 @@ if DISPLAY
 config INPUT_FT5336_INTERRUPT
 	default y
 
-
 if LVGL
 
 config LV_Z_VDB_SIZE
@@ -116,9 +98,15 @@ endif # LVGL
 
 endif # DISPLAY
 
-endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
+endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
 
-if BOARD_BL5340_DVK_CPUNET
+config IPM_NRFX
+	default IPM
+
+config MBOX_NRFX_IPC
+	default MBOX
+
+if BOARD_BL5340_DVK_NRF5340_CPUNET
 
 # BT_CTLR depends on BT. When BT is enabled we should default to also
 # enabling the controller.
@@ -128,4 +116,4 @@ config BT_CTLR
 config BT_ECC
 	default y if BT
 
-endif # BOARD_BL5340_DVK_CPUNET
+endif # BOARD_BL5340_DVK_NRF5340_CPUNET

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include <nordic/nrf5340_cpuapp_qkaa.dtsi>
-#include "bl5340_dvk_cpuapp_common.dtsi"
+#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi"
 
 / {
 	model = "Laird Connectivity BL5340 (nRF5340) Application";

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml

@@ -1,4 +1,4 @@
-identifier: bl5340_dvk_cpuapp
+identifier: bl5340_dvk/nrf5340/cpuapp
 name: BL5340-DVK-application-MCU
 type: mcu
 arch: arm

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi

@@ -4,7 +4,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "bl5340_dvk_cpuapp_common-pinctrl.dtsi"
+#include "bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
@@ -378,4 +378,4 @@
 };
 
 /* Include partition configuration file */
-#include "bl5340_dvk_cpuapp_partition_conf.dtsi"
+#include "bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi"

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig

@@ -1,9 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_NRF53X=y
-CONFIG_SOC_NRF5340_CPUAPP_QKAA=y
-CONFIG_BOARD_BL5340_DVK_CPUAPP=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include <nordic/nrf5340_cpuappns_qkaa.dtsi>
-#include "bl5340_dvk_cpuapp_common.dtsi"
+#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi"
 
 / {
 	model = "Laird Connectivity BL5340 (nRF5340) Application";

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml

@@ -1,4 +1,4 @@
-identifier: bl5340_dvk_cpuapp_ns
+identifier: bl5340_dvk/nrf5340/cpuapp/ns
 name: BL5340-DVK-application-MCU-Non-Secure
 type: mcu
 arch: arm

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig

@@ -1,9 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_NRF53X=y
-CONFIG_SOC_NRF5340_CPUAPP_QKAA=y
-CONFIG_BOARD_BL5340_DVK_CPUAPP_NS=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 
@@ -13,7 +9,7 @@ CONFIG_HW_STACK_PROTECTION=y
 # Enable TrustZone-M
 CONFIG_ARM_TRUSTZONE_M=y
 
-# This Board implies building Non-Secure firmware
+# This board implies building Non-Secure firmware
 CONFIG_TRUSTED_EXECUTION_NONSECURE=y
 
 # Enable GPIO

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi

@@ -58,4 +58,4 @@
 };
 
 /* Include shared RAM configuration file */
-#include "bl5340_dvk_shared_sram_planning_conf.dtsi"
+#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi"

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts

@@ -6,8 +6,8 @@
 
 /dts-v1/;
 #include <nordic/nrf5340_cpunet_qkaa.dtsi>
-#include "bl5340_dvk_cpunet-pinctrl.dtsi"
-#include "bl5340_dvk_cpunet_common.dtsi"
+#include "bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi"
+#include "bl5340_dvk_nrf5340_cpunet_common.dtsi"
 
 / {
 	model = "Laird Connectivity BL5340 (nRF5340) Network";

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml

@@ -1,4 +1,4 @@
-identifier: bl5340_dvk_cpunet
+identifier: bl5340_dvk/nrf5340/cpunet
 name: BL5340-DVK-network-MCU
 type: mcu
 arch: arm

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi

@@ -64,4 +64,4 @@
 };
 
 /* Include shared RAM configuration file */
-#include "bl5340_dvk_shared_sram_planning_conf.dtsi"
+#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi"

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig

@@ -1,9 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_NRF53X=y
-CONFIG_SOC_NRF5340_CPUNET_QKAA=y
-CONFIG_BOARD_BL5340_DVK_CPUNET=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/laird_connect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig

@@ -0,0 +1 @@
+# SPDX-License-Identifier: Apache-2.0

boards/laird_connect/bl5340_dvk/board.cmake

@@ -2,21 +2,20 @@
 # Copyright (c) 2021 Laird Connectivity
 # SPDX-License-Identifier: Apache-2.0
 
-if(CONFIG_BOARD_BL5340_DVK_CPUAPP_NS)
+if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS)
   set(TFM_PUBLIC_KEY_FORMAT "full")
 endif()
 
-if(CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPP_NS)
-board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
+if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS)
+  board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
+elseif(BOARD_BL5340_DVK_NRF5340_CPUNET)
+  board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
 endif()
 
 if(CONFIG_TFM_FLASH_MERGED_BINARY)
   set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
 endif()
 
-if(CONFIG_BOARD_BL5340_DVK_CPUNET)
-board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
-endif()
-
 include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/laird_connect/bl5340_dvk/board.yml

@@ -0,0 +1,8 @@
+board:
+  name: bl5340_dvk
+  vendor: Laird Connectivity
+  socs:
+  - name: 'nrf5340'
+    variants:
+    - name: 'ns'
+      cpucluster: 'cpuapp'

boards/laird_connect/bl5340_dvk/doc/index.rst

@@ -16,10 +16,10 @@ dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
 * a secondary Arm Cortex-M33 core, with a reduced feature set, running
   at a fixed 64 MHz, referred to as the **network core**.
 
-The bl5340_dvk_cpuapp build target provides support for the application
-core on the BL5340 module. The bl5340_dvk_cpunet build target provides
+The ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the application
+core on the BL5340 module. The ``bl5340_dvk/nrf5340/cpunet`` build target provides
 support for the network core on the BL5340 module. If ARM TrustZone is
-used then the bl5340_dvk_cpuapp build target provides support for the
+used then the ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the
 non-secure partition of the application core on the BL5340 module.
 
 This development kit has the following features:
@@ -65,7 +65,7 @@ is 32MHz.
 Supported Features
 ==================
 
-The bl5340_dvk_cpuapp board configuration supports the following
+The ``bl5340_dvk/nrf5340/cpuapp`` board configuration supports the following
 hardware features:
 
 +-----------+------------+----------------------+
@@ -104,7 +104,7 @@ hardware features:
 | WDT       | on-chip    | watchdog             |
 +-----------+------------+----------------------+
 
-The bl5340_dvk_cpunet board configuration supports the following
+The ``bl5340_dvk/nrf5340/cpunet`` board configuration supports the following
 hardware features:
 
 +-----------+------------+----------------------+
@@ -271,7 +271,7 @@ Programming and Debugging
 *************************
 
 The BL5340's application core supports the Armv8-M Security Extension.
-Applications built for the bl5340_dvk_cpuapp board by default
+Applications built for the ``bl5340_dvk/nrf5340/cpuapp`` board by default
 boot in the Secure state.
 
 The BL5340's network core does not support the Armv8-M Security
@@ -300,7 +300,7 @@ The process to build the Secure firmware image using TF-M and the
 Non-Secure firmware image using Zephyr requires the following steps:
 
 1. Build the Non-Secure Zephyr application
-   for the application core using ``-DBOARD=bl5340_dvk_cpuapp_ns``.
+   for the application core using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``.
    To invoke the building of TF-M the Zephyr build system requires the
    Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by
    default when building Zephyr as a Non-Secure application.
@@ -318,7 +318,7 @@ Non-Secure firmware image using Zephyr requires the following steps:
    address and sizes.
 
 2. Build the application firmware for the network core using
-   ``-DBOARD=bl5340_dvk_cpunet``.
+   ``-DBOARD=bl5340_dvk/nrf5340/cpunet``.
 
 Building the Secure firmware using Zephyr
 -----------------------------------------
@@ -327,14 +327,14 @@ The process to build the Secure and the Non-Secure firmware images
 using Zephyr requires the following steps:
 
 1. Build the Secure Zephyr application for the application core
-   using ``-DBOARD=bl5340_dvk_cpuapp`` and
+   using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` and
    ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n``
    in the application project configuration file.
 2. Build the Non-Secure Zephyr application for the application core
-   using ``-DBOARD=bl5340_dvk_cpuapp_ns``.
+   using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``.
 3. Merge the two binaries together.
 4. Build the application firmware for the network core using
-   ``-DBOARD=bl5340_dvk_cpunet``.
+   ``-DBOARD=bl5340_dvk/nrf5340/cpunet``.
 
 When building a Secure/Non-Secure application for the BL5340's
 application core, the Secure application will have to set the IDAU
@@ -346,9 +346,9 @@ Building a Secure only application
 ==================================
 
 Build the Zephyr app in the usual way (see :ref:`build_an_application`
-and :ref:`application_run`), using ``-DBOARD=bl5340_dvk_cpuapp`` for
+and :ref:`application_run`), using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` for
 the firmware running on the BL5340's application core, and using
-``-DBOARD=bl5340_dvk_cpunet`` for the firmware running
+``-DBOARD=bl5340_dvk/nrf5340/cpunet`` for the firmware running
 on the BL5340's network core.
 
 Flashing
@@ -395,7 +395,7 @@ Then build and flash the application in the usual way.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: bl5340_dvk_cpuapp
+   :board: bl5340_dvk/nrf5340/cpuapp
    :goals: build flash
 
 Debugging