soc: convert microchip_mec to hwmv2

Convert the Microchip MEC soc/ to hardware model v2.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>

drivers/ps2/Kconfig.xec

@@ -5,7 +5,7 @@
 
 config PS2_XEC
 	bool "XEC Microchip PS2 driver"
-	depends on SOC_FAMILY_MEC && ESPI_PERIPHERAL_8042_KBC
+	depends on SOC_FAMILY_MICROCHIP_MEC && ESPI_PERIPHERAL_8042_KBC
 	select PINCTRL
 	help
 	  Enable the Microchip XEC PS2 IO driver. The driver also

drivers/sensor/mchp_tach_xec/Kconfig

@@ -7,7 +7,7 @@ config TACH_XEC
 	bool "XEC Tachometer sensor"
 	default y
 	depends on DT_HAS_MICROCHIP_XEC_TACH_ENABLED
-	depends on SOC_FAMILY_MEC
+	depends on SOC_FAMILY_MICROCHIP_MEC
 	select PINCTRL
 	help
 	  Enable the Microchip XEC tachometer sensor.

soc/microchip/mec/Kconfig

@@ -4,13 +4,7 @@
 # Copyright (c) 2022, Microchip Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_FAMILY_MEC
-	bool
-
-if SOC_FAMILY_MEC
-config SOC_FAMILY
-	string
-	default "microchip_mec"
+if SOC_FAMILY_MICROCHIP_MEC
 
 menuconfig MCHP_MEC_UNSIGNED_HEADER
 	bool "Create an unsigned output binary with MCHP MEC binary header"
@@ -216,7 +210,17 @@ config MCHP_HEADER_VERBOSE_OUTPUT
 
 endif # MCHP_MEC_UNSIGNED_HEADER
 
-# Select SoC Part No. and configuration options
-source "soc/soc_legacy/arm/microchip_mec/*/Kconfig.soc"
+config SOC_MEC172X_PROC_CLK_DIV
+	int "PROC_CLK_DIV"
+	default 1
+	range 1 48
+	help
+	  This divisor defines a ratio between processor clock (HCLK)
+	  and main 96 MHz clock (MCK):
+	  HCLK = MCK / PROC_CLK_DIV
+	  Allowed divider values: 1, 3, 4, 16, and 48.
 
-endif # SOC_FAMILY_MEC
+# Select SoC Part No. and configuration options
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_MICROCHIP_MEC

soc/microchip/mec/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_MICROCHIP_MEC
+
+rsource "*/Kconfig.defconfig.series"
+
+endif # SOC_FAMILY_MICROCHIP_MEC

soc/microchip/mec/Kconfig.soc

@@ -0,0 +1,12 @@
+# Microchip MEC172x, MEC1501 MCU line
+
+# Copyright (c) 2018 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MICROCHIP_MEC
+	bool
+
+config SOC_FAMILY
+	default "microchip_mec" if SOC_FAMILY_MICROCHIP_MEC
+
+rsource "*/Kconfig.soc"

soc/microchip/mec/common/CMakeLists.txt

@@ -12,7 +12,7 @@ endif()
 if (DEFINED CONFIG_MCHP_MEC_UNSIGNED_HEADER)
   set(MCHP_MEC_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.mchp.bin)
   set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-    COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/spigen/mec_spi_gen.py
+    COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/microchip/mec/common/spigen/mec_spi_gen.py
     -i ${KERNEL_BIN_NAME}
     -o ${MCHP_MEC_BIN_NAME}
     -c ${CONFIG_MCHP_MEC_HEADER_CHIP}

soc/microchip/mec/mec1501x/CMakeLists.txt

@@ -4,9 +4,8 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-zephyr_sources(
-  soc.c
-  )
+zephyr_sources(soc.c)
+zephyr_include_directories(.)
 
 zephyr_sources_ifdef(CONFIG_PM
   device_power.c

soc/microchip/mec/mec1501x/Kconfig

@@ -3,15 +3,17 @@
 # Copyright (c) 2018 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-choice
-	prompt "MEC1501 Selection"
-	depends on SOC_SERIES_MEC1501X
+config SOC_SERIES_MEC1501X
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_ARM_MPU
+	select HAS_PM
 
 config SOC_MEC1501_HSZ
-	bool "MEC1501_HSZ"
 	select HAS_MEC_HAL
 
-endchoice
+if SOC_SERIES_MEC1501X
 
 config RTOS_TIMER
 	bool "MEC1501 RTOS timer"
@@ -95,3 +97,5 @@ config GPIO_INIT_PRIORITY
 	default 41
 
 endif # GPIO
+
+endif # SOC_SERIES_MEC1501X

soc/microchip/mec/mec1501x/Kconfig.defconfig.mec1501hsz

@@ -5,9 +5,6 @@
 
 if SOC_MEC1501_HSZ
 
-config SOC
-	default "mec1501hsz"
-
 config GPIO
 	default y
 

soc/microchip/mec/mec1501x/Kconfig.defconfig.series

@@ -5,16 +5,13 @@
 
 if SOC_SERIES_MEC1501X
 
-config SOC_SERIES
-	default "mec1501"
-
 config NUM_IRQS
 	# must be >= the highest interrupt number used
 	# - include the UART interrupts
 	# All NVIC external sources.
 	default 174
 
-source "soc/soc_legacy/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501*"
+rsource "Kconfig.defconfig.mec1501*"
 
 if RTOS_TIMER
 

soc/microchip/mec/mec1501x/Kconfig.soc

@@ -0,0 +1,20 @@
+# Microchip MEC1501 MCU core series
+
+# Copyright (c) 2018 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MEC1501X
+	bool
+	select SOC_FAMILY_MICROCHIP_MEC
+	help
+	  Enable support for Microchip MEC Cortex-M4 MCU series
+
+config SOC_SERIES
+	default "mec1501x" if SOC_SERIES_MEC1501X
+
+config SOC_MEC1501_HSZ
+	bool
+	select SOC_SERIES_MEC1501X
+
+config SOC
+	default "mec1501hsz" if SOC_MEC1501_HSZ

soc/microchip/mec/mec172x/CMakeLists.txt

@@ -5,9 +5,8 @@
 #
 
 zephyr_include_directories(${ZEPHYR_BASE}/drivers)
-zephyr_sources(
-  soc.c
-  )
+zephyr_sources(soc.c)
+zephyr_include_directories(.)
 
 if(CONFIG_PM)
   zephyr_library_sources(power.c device_power.c)

soc/microchip/mec/mec172x/Kconfig

@@ -1,32 +1,22 @@
-# Microchip MEC172x MCU core series
+# Microchip MEC172X MCU core series
 
 # Copyright (c) 2021 Microchip Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-choice
-	prompt "MEC172x Selection"
-	depends on SOC_SERIES_MEC172X
+config SOC_SERIES_MEC172X
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select HAS_SWO
+	select HAS_PM
 
-config SOC_MEC172X_NSZ
-	bool "MEC172X_NSZ"
-config SOC_MEC172X_NLJ
-	bool "MEC172X_NLJ"
-
-endchoice
+if SOC_SERIES_MEC172X
 
 config RTOS_TIMER
 	bool "MEC172x RTOS Timer(32KHz) as kernel timer"
 
-config SOC_MEC172X_PROC_CLK_DIV
-	int "PROC_CLK_DIV"
-	default 1
-	range 1 48
-	help
-	  This divisor defines a ratio between processor clock (HCLK)
-	  and main 96 MHz clock (MCK):
-	  HCLK = MCK / PROC_CLK_DIV
-	  Allowed divider values: 1, 3, 4, 16, and 48.
-
 choice
 	prompt "MEC172x debug interface general configuration"
 	default SOC_MEC172X_DEBUG_WITHOUT_TRACING
@@ -82,3 +72,5 @@ config GPIO_INIT_PRIORITY
 	default 41
 
 endif # GPIO
+
+endif # SOC_SERIES_MEC172X

soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj

@@ -5,9 +5,6 @@
 
 if SOC_MEC172X_NLJ
 
-config SOC
-	default "mec172xnlj"
-
 config GPIO
 	default y
 

soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz

@@ -5,9 +5,6 @@
 
 if SOC_MEC172X_NSZ
 
-config SOC
-	default "mec172xnsz"
-
 config GPIO
 	default y
 

soc/microchip/mec/mec172x/Kconfig.defconfig.series

@@ -5,16 +5,13 @@
 
 if SOC_SERIES_MEC172X
 
-config SOC_SERIES
-	default "mec172x"
-
 config NUM_IRQS
 	# must be >= the highest interrupt number used
 	# - include the UART interrupts
 	# All NVIC external sources.
 	default 181
 
-source "soc/soc_legacy/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172x*"
+rsource "Kconfig.defconfig.mec172x*"
 
 if RTOS_TIMER
 

soc/microchip/mec/mec172x/Kconfig.soc

@@ -0,0 +1,25 @@
+# Microchip MEC172x MCU core series
+
+# Copyright (c) 2021 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MEC172X
+	bool
+	select SOC_FAMILY_MICROCHIP_MEC
+	help
+	  Enable support for Microchip MEC Cortex-M4F MCU series
+
+config SOC_SERIES
+	default "mec172x" if SOC_SERIES_MEC172X
+
+config SOC_MEC172X_NSZ
+	bool
+	select SOC_SERIES_MEC172X
+
+config SOC_MEC172X_NLJ
+	bool
+	select SOC_SERIES_MEC172X
+
+config SOC
+	default "mec172xnsz" if SOC_MEC172X_NSZ
+	default "mec172xnlj" if SOC_MEC172X_NLJ

soc/microchip/mec/soc.yml

@@ -0,0 +1,10 @@
+family:
+- name: microchip_mec
+  series:
+  - name: mec1501x
+    socs:
+    - name: mec1501_hsz
+  - name: mec172x
+    socs:
+    - name: mec172x_nsz
+    - name: mec172x_nlj

soc/soc_legacy/arm/microchip_mec/Kconfig.defconfig

@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/arm/microchip_mec/*/Kconfig.defconfig.series"

soc/soc_legacy/arm/microchip_mec/Kconfig.soc

@@ -1,6 +0,0 @@
-# Microchip MEC172x, MEC1501 MCU line
-
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/arm/microchip_mec/*/Kconfig.series"

soc/soc_legacy/arm/microchip_mec/mec1501/Kconfig.series

@@ -1,15 +0,0 @@
-# Microchip MEC1501 MCU core series
-
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_MEC1501X
-	bool "Microchip MEC1501X Series"
-	select ARM
-	select CPU_CORTEX_M4
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_ARM_MPU
-	select SOC_FAMILY_MEC
-	select HAS_PM
-	help
-	  Enable support for Microchip MEC Cortex-M4 MCU series

soc/soc_legacy/arm/microchip_mec/mec172x/Kconfig.series

@@ -1,17 +0,0 @@
-# Microchip MEC172X MCU core series
-
-# Copyright (c) 2021 Microchip Technology Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_MEC172X
-	bool "Microchip MEC172X Series"
-	select ARM
-	select CPU_CORTEX_M4
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select CPU_HAS_ARM_MPU
-	select SOC_FAMILY_MEC
-	select HAS_SWO
-	select HAS_PM
-	help
-	  Enable support for Microchip MEC Cortex-M4F MCU series