boards: xtensa: intel_adsp_ace20_lnl: move and convert to HWMv2

Move and convert to HWMv2 intel_adsp_ace20_lnl board configuration.

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>

boards/boards_legacy/xtensa/intel_adsp_ace20_lnl/Kconfig.board

@@ -1,8 +0,0 @@
-# Xtensa board configuration
-
-# Copyright (c) 2022 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config  BOARD_INTEL_ADSP_ACE20_LNL
-	bool "Intel ADSP ACE 2.0 Lunar Lake PCH"
-	depends on SOC_SERIES_INTEL_ACE

boards/boards_legacy/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig

@@ -1,10 +0,0 @@
-# Copyright (c) 2022 Intel Corporation
-#
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_INTEL_ADSP_ACE20_LNL
-
-config BOARD
-	default "intel_adsp_ace20_lnl"
-
-endif # BOARD_INTEL_ADSP_ACE20_LNL

boards/intel/intel_adsp_ace20_lnl/Kconfig.intel_adsp_ace20_lnl

@@ -0,0 +1,5 @@
+# Copyright (c) 2022-2024 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_ADSP_ACE20_LNL
+	select SOC_INTEL_ACE20_LNL

boards/intel/intel_adsp_ace20_lnl/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: intel_adsp_ace20_lnl
+  vendor: intel
+  socs:
+    - name: intel_ace20_lnl

boards/intel/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig

@@ -2,10 +2,6 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_ACE=y
-CONFIG_SOC_INTEL_ACE20_LNL=y
-CONFIG_BOARD_INTEL_ADSP_ACE20_LNL=y
-
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n