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boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2

Browse Source 
This commit converts the SiFive HiFive1 Rev. B board (`hifive1_revb`
target) to the Zephyr Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski
2024-02-19 14:12:27 +01:00
committed by Carles Cufi
parent 330fc38f9f
commit bfcc2ed18f
25 changed files with 117 additions and 359 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
boards/boards_legacy/riscv/hifive1_revb/Kconfig.board
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@@ -1,6 +0,0 @@
# Copyright (c) 2019 SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
config BOARD_HIFIVE1_REVB
bool "HiFive1 Rev B target"
depends on SOC_SIFIVE_FREEDOM_E340

21
boards/boards_legacy/riscv/hifive1_revb/Kconfig.defconfig
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@@ -1,21 +0,0 @@
# Copyright (c) 2019 SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
if BOARD_HIFIVE1_REVB
config BOARD
default "hifive1_revb"
config HAS_FLASH_LOAD_OFFSET
default y
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/spi@10014000,1)
config FLASH_LOAD_OFFSET
default 0x0
config SYS_CLOCK_TICKS_PER_SEC
default 128
endif

8
boards/boards_legacy/riscv/hifive1_revb/board.cmake
View File

@@ -1,8 +0,0 @@
# Copyright (c) 2019 SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
board_runner_args(jlink "--device=FE310")
board_runner_args(jlink "--iface=JTAG")
board_runner_args(jlink "--speed=4000")
board_runner_args(jlink "--tool-opt=-jtagconf -1,-1")
board_runner_args(jlink "--tool-opt=-autoconnect 1")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

49
boards/boards_legacy/riscv/hifive1_revb/doc/index.rst
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@@ -1,49 +0,0 @@
.. _hifive1_revb:
SiFive HiFive1 Rev B
####################
Overview
********
The HiFive1 Rev B is an Arduino-compatible development board with
a SiFive FE310-G002 RISC-V SoC.
.. image:: img/hifive1_revb.jpg
:align: center
:alt: SiFive HiFive1 Rev B board
Programming and debugging
*************************
Building
========
Applications for the ``hifive1_revb`` board configuration can be built as usual
(see :ref:`build_an_application`) using the corresponding board name:
.. zephyr-app-commands::
:board: hifive1_revb
:goals: build
Flashing
========
The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and
debug the board, you'll need to install the
`Segger J-Link Software and Documentation Pack
<https://www.segger.com/downloads/jlink#J-LinkSoftwareAndDocumentationPack>`_
and choose version V6.46a or later (Downloads for Windows, Linux, and macOS are
available).
With the Segger J-Link Software installed, you can flash the application as usual
(see :ref:`build_an_application` and :ref:`application_run` for more details):
.. code-block:: console
west flash
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.

87
boards/boards_legacy/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi
View File

@@ -1,87 +0,0 @@
/*
* Copyright (c) 2022 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/pinctrl/sifive-pinctrl.h>
&pinctrl {
/* UART0 */
uart0_rx_default: uart0_rx_default {
pinmux = <16 SIFIVE_PINMUX_IOF0>;
};
uart0_tx_default: uart0_tx_default {
pinmux = <17 SIFIVE_PINMUX_IOF0>;
};
/* SPI1 */
spi1_cs0_default: spi1_cs0_default {
pinmux = <2 SIFIVE_PINMUX_IOF0>;
};
spi1_mosi_default: spi1_mosi_default {
pinmux = <3 SIFIVE_PINMUX_IOF0>;
};
spi1_miso_default: spi1_miso_default {
pinmux = <4 SIFIVE_PINMUX_IOF0>;
};
spi1_sck_default: spi1_sck_default {
pinmux = <5 SIFIVE_PINMUX_IOF0>;
};
spi1_cs2_default: spi1_cs2_default {
pinmux = <9 SIFIVE_PINMUX_IOF0>;
};
spi1_cs3_default: spi1_cs3_default {
pinmux = <10 SIFIVE_PINMUX_IOF0>;
};
/* PWM0 */
pwm0_0_default: pwm0_0_default {
pinmux = <0 SIFIVE_PINMUX_IOF1>;
};
pwm0_1_default: pwm0_1_default {
pinmux = <1 SIFIVE_PINMUX_IOF1>;
};
pwm0_2_default: pwm0_2_default {
pinmux = <2 SIFIVE_PINMUX_IOF1>;
};
pwm0_3_default: pwm0_3_default {
pinmux = <3 SIFIVE_PINMUX_IOF1>;
};
/* PWM1 */
pwm1_0_default: pwm1_0_default {
pinmux = <20 SIFIVE_PINMUX_IOF1>;
};
pwm1_1_default: pwm1_1_default {
pinmux = <19 SIFIVE_PINMUX_IOF1>;
};
pwm1_2_default: pwm1_2_default {
pinmux = <21 SIFIVE_PINMUX_IOF1>;
};
pwm1_3_default: pwm1_3_default {
pinmux = <22 SIFIVE_PINMUX_IOF1>;
};
/* PWM2 */
pwm2_0_default: pwm2_0_default {
pinmux = <10 SIFIVE_PINMUX_IOF1>;
};
pwm2_1_default: pwm2_1_default {
pinmux = <11 SIFIVE_PINMUX_IOF1>;
};
pwm2_2_default: pwm2_2_default {
pinmux = <12 SIFIVE_PINMUX_IOF1>;
};
pwm2_3_default: pwm2_3_default {
pinmux = <13 SIFIVE_PINMUX_IOF1>;
};
/* I2C0 */
i2c0_0_default: i2c0_0_default {
pinmux = <12 SIFIVE_PINMUX_IOF0>;
};
i2c0_1_default: i2c0_1_default {
pinmux = <13 SIFIVE_PINMUX_IOF0>;
};
};

143
boards/boards_legacy/riscv/hifive1_revb/hifive1_revb.dts
View File

@@ -1,143 +0,0 @@
/* Copyright (c) 2019 SiFive, Inc. */
/* SPDX-License-Identifier: Apache-2.0 */
/dts-v1/;
#include <sifive/riscv32-fe310.dtsi>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include "hifive1_revb-pinctrl.dtsi"
/ {
model = "SiFive HiFive 1 Rev B";
compatible = "sifive,hifive1-revb";
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
watchdog0 = &wdog0;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &dtim;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
led1: led_1 {
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
led2: led_2 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = /* A0 not connected */
<1 0 &gpio0 9 0>, /* A1, also CS2 */
<2 0 &gpio0 10 0>, /* A2, also WF_INT */
<3 0 &gpio0 11 0>, /* A3 */
<4 0 &gpio0 12 0>, /* A4 */
<5 0 &gpio0 13 0>, /* A5 */
<6 0 &gpio0 16 0>, /* D0, also TX */
<7 0 &gpio0 17 0>, /* D1, also RX */
<8 0 &gpio0 18 0>, /* D2 */
<9 0 &gpio0 19 0>, /* D3 */
<10 0 &gpio0 20 0>, /* D4 */
<11 0 &gpio0 21 0>, /* D5 */
<12 0 &gpio0 22 0>, /* D6 */
<13 0 &gpio0 23 0>, /* D7 */
<14 0 &gpio0 0 0>, /* D8 */
<15 0 &gpio0 1 0>, /* D9 */
<16 0 &gpio0 2 0>, /* D10 */
<17 0 &gpio0 3 0>, /* D11, also MOSI */
<18 0 &gpio0 4 0>, /* D12, also MISO */
<19 0 &gpio0 5 0>, /* D13, also SCK */
<20 0 &gpio0 12 0>, /* D14, also SDA */
<21 0 &gpio0 13 0>; /* D15, also SCL */
};
};
&coreclk {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
pinctrl-names = "default";
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
/* disabled (used by Flash ROM by default) */
&spi0 {
reg = <0x10014000 0x1000 0x20010000 0x3c0900>;
flash0: flash@0 {
compatible = "issi,is25lp128", "jedec,spi-nor";
status = "disabled";
size = <134217728>;
jedec-id = [96 60 18];
reg = <0>;
spi-max-frequency = <133000000>;
};
};
&spi1 {
status = "okay";
pinctrl-0 = <&spi1_cs0_default
&spi1_mosi_default
&spi1_miso_default
&spi1_sck_default>;
pinctrl-names = "default";
};
&spi2 {
status = "okay";
pinctrl-0 = <&spi1_cs2_default
&spi1_mosi_default
&spi1_miso_default
&spi1_sck_default>;
pinctrl-names = "default";
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
arduino_i2c: &i2c0 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_0_default &i2c0_1_default>;
pinctrl-names = "default";
};

10
boards/boards_legacy/riscv/hifive1_revb/hifive1_revb_defconfig
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@@ -1,10 +0,0 @@
CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y
CONFIG_SOC_SIFIVE_FREEDOM_E340=y
CONFIG_BOARD_HIFIVE1_REVB=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_RISCV_CORE_E31=y

5
boards/sifive/hifive1/Kconfig Normal file
View File

@@ -0,0 +1,5 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config BOARD_HIFIVE1
select RISCV_CORE_E31 if "$(BOARD_REVISION)" = "B"

13
boards/sifive/hifive1/Kconfig.defconfig
View File

@@ -5,4 +5,17 @@ if BOARD_HIFIVE1_FE310
config SYS_CLOCK_TICKS_PER_SEC
default 128
if "$(BOARD_REVISION)" = "B"
config HAS_FLASH_LOAD_OFFSET
default y
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/spi@10014000,1)
config FLASH_LOAD_OFFSET
default 0x0
endif # "$(BOARD_REVISION)" = "B"
endif # BOARD_HIFIVE1_FE310

23
boards/sifive/hifive1/board.cmake
View File

@@ -12,11 +12,18 @@ set(QEMU_FLAGS_${ARCH}
-machine sifive_e
)
board_set_flasher_ifnset(hifive1)
board_finalize_runner_args(hifive1)
board_runner_args(openocd --cmd-load "hifive1-load")
board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt")
board_runner_args(openocd --cmd-post-verify "hifive1-post-verify")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
if("${BOARD_REVISION}" STREQUAL "A")
board_set_flasher_ifnset(hifive1)
board_finalize_runner_args(hifive1)
board_runner_args(openocd --cmd-load "hifive1-load")
board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt")
board_runner_args(openocd --cmd-post-verify "hifive1-post-verify")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
elseif("${BOARD_REVISION}" STREQUAL "B")
board_runner_args(jlink "--device=FE310")
board_runner_args(jlink "--iface=JTAG")
board_runner_args(jlink "--speed=4000")
board_runner_args(jlink "--tool-opt=-jtagconf -1,-1")
board_runner_args(jlink "--tool-opt=-autoconnect 1")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
endif()

0
boards/boards_legacy/riscv/hifive1_revb/doc/img/hifive1_revb.jpg → boards/sifive/hifive1/doc/img/hifive1_revb.jpg
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Side by Side Swipe Overlay

Before

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After

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75
boards/sifive/hifive1/doc/index.rst
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@@ -7,9 +7,9 @@ Overview
********
The HiFive1 is an Arduino-compatible development board with
an FE310 RISC-V SoC.
More information can be found on
`SiFive's website <https://www.sifive.com/boards/hifive1>`_.
an FE310 RISC-V SoC. Two revisions of this board are supported in Zephyr:
`HiFive1 <https://www.sifive.com/boards/hifive1>`__ (also known as HiFive1 Rev A)
and `HiFive1 Rev B <https://www.sifive.com/boards/hifive1-rev-b>`__.
.. figure:: img/hifive1.jpg
:align: center
@@ -17,44 +17,77 @@ More information can be found on
SiFive HiFive1 board (image courtesy of SiFive)
.. figure:: img/hifive1_revb.jpg
:align: center
:alt: SiFive HiFive1 Rev B board
SiFive HiFive1 Rev B board (image courtesy of SiFive)
Programming and debugging
*************************
Building
========
Applications for the ``hifive1`` board configuration can be built as usual
(see :ref:`build_an_application`) using the corresponding board name:
Applications for the HiFive1 board configuration can be built as usual (see
:ref:`build_an_application`) using the corresponding board name:
.. zephyr-app-commands::
:board: hifive1
:goals: build
.. tabs::
.. group-tab:: HiFive1
.. zephyr-app-commands::
:board: hifive1
:goals: build
.. group-tab:: HiFive1 Rev B
.. zephyr-app-commands::
:board: hifive1@B
:goals: build
Flashing
========
In order to upload the application to the device, you'll need OpenOCD with
RISC-V support. Download the tarball for your OS from the `SiFive website
<https://www.sifive.com/boards>`_ and extract it.
The Zephyr SDK uses a bundled version of OpenOCD by default. You can
overwrite that behavior by adding the
``-DOPENOCD=<path/to/riscv-openocd/bin/openocd>`` parameter when building:
HiFive1
-------
.. zephyr-app-commands::
:board: hifive1
:goals: build
:gen-args: -DOPENOCD=<path/to/riscv-openocd/bin/openocd>
.. tabs::
When using a custom toolchain it should be enough to have the downloaded
version of the binary in your ``PATH``.
.. group-tab:: HiFive1
In order to upload the application to the device, you'll need OpenOCD with
RISC-V support. Download the tarball for your OS from the `SiFive website
<https://www.sifive.com/boards>`_ and extract it.
The Zephyr SDK uses a bundled version of OpenOCD by default. You can
overwrite that behavior by adding the
``-DOPENOCD=<path/to/riscv-openocd/bin/openocd>`` parameter when building:
.. zephyr-app-commands::
:board: hifive1
:goals: build
:gen-args: -DOPENOCD=<path/to/riscv-openocd/bin/openocd>
When using a custom toolchain it should be enough to have the downloaded
version of the binary in your ``PATH``.
.. group-tab:: HiFive1 Rev B
The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and
debug the board, you'll need to install the
`Segger J-Link Software and Documentation Pack
<https://www.segger.com/downloads/jlink#J-LinkSoftwareAndDocumentationPack>`_
and choose version V6.46a or later (Downloads for Windows, Linux, and macOS are
available).
Now you can flash the application as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details):
.. code-block:: console
ninja flash
west flash
Depending on your OS you might have to run the flash command as superuser.

1
boards/sifive/hifive1/hifive1_defconfig
View File

@@ -6,4 +6,3 @@ CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_PINCTRL=y
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y

1
boards/sifive/hifive1/hifive1_fe310_A_defconfig Normal file
View File

@@ -0,0 +1 @@
CONFIG_BUILD_OUTPUT_HEX=y

24
boards/sifive/hifive1/hifive1_fe310_B.overlay Normal file
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@@ -0,0 +1,24 @@
/*
* Copyright (c) 2024 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
model = "SiFive HiFive 1 Rev. B";
compatible = "sifive,hifive1_revb";
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
&spi2 {
status = "okay";
pinctrl-0 = <&spi1_cs2_default
&spi1_mosi_default
&spi1_miso_default
&spi1_sck_default>;
pinctrl-names = "default";
};

2
boards/boards_legacy/riscv/hifive1_revb/hifive1_revb.yaml → boards/sifive/hifive1/hifive1_fe310_B.yaml
View File

@@ -1,4 +1,4 @@
identifier: hifive1_revb
identifier: hifive1@B
name: SiFive HiFive1 Rev B
type: mcu
arch: riscv

2
samples/subsys/zbus/benchmark/benchmark_256KB.robot
View File

@@ -9,7 +9,7 @@ Suite Teardown Terminate All Processes kill=True
*** Variables ***
${csv_file} zbus_dyn_benchmark_256kb.csv
${board} hifive1_revb
${board} hifive1@B
${serial_port} /dev/ttyACM0

0
samples/subsys/zbus/remote_mock/boards/hifive1_revb.conf → samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.conf
View File

0
samples/subsys/zbus/remote_mock/boards/hifive1_revb.overlay → samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.overlay
View File

2
samples/subsys/zbus/remote_mock/sample.yaml
View File

@@ -7,6 +7,6 @@ tests:
platform_allow:
- native_posix
- native_sim
- hifive1_revb
- hifive1@B
integration_platforms:
- native_sim

0
samples/subsys/zbus/uart_bridge/boards/hifive1_revb.conf → samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.conf
View File

0
samples/subsys/zbus/uart_bridge/boards/hifive1_revb.overlay → samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.overlay
View File

2
samples/userspace/syscall_perf/sample.yaml
View File

@@ -13,4 +13,4 @@ tests:
filter: CONFIG_ARCH_HAS_USERSPACE
arch_allow: riscv
integration_platforms:
- hifive1_revb
- hifive1@B

2
tests/drivers/build_all/pwm/testcase.yaml
View File

@@ -27,7 +27,7 @@ tests:
drivers.pwm.rv32m1.tpm.build:
platform_allow: rv32m1_vega/openisa_rv32m1/ri5cy
drivers.pwm.sifive.build:
platform_allow: hifive1_revb
platform_allow: hifive1@B
drivers.pwm.npcx.build:
platform_allow: npcx7m6fb_evb
drivers.pwm.nrf.sw.build:

0
tests/drivers/gpio/gpio_basic_api/boards/hifive1_revb.overlay → tests/drivers/gpio/gpio_basic_api/boards/hifive1_fe310_B.overlay
View File