soc: mec: rename all mec1501x reference to mec15xx

Fix a bunch of references to "mec1501x" to be named "mec15xx" instead,
which is better representative of what is supported and also matches the
soc series name and value.

Fix the clock div option name as well while at it since it apparently
applies to the whole family.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>

boards/microchip/mec172xevb_assy6906/Kconfig.defconfig

@@ -22,7 +22,7 @@ if !RTOS_TIMER
 # If RTOS timer is not enabled we use ARM Cortex-M
 # SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
 # processor clock divider register. We assume PCR processor clock divider
-# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV
+# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV
 #
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC

boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig

@@ -22,7 +22,7 @@ if !RTOS_TIMER
 # If RTOS timer is not enabled we use ARM Cortex-M
 # SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
 # processor clock divider register. We assume PCR processor clock divider
-# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV
+# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV
 #
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC

drivers/clock_control/clock_control_mchp_xec.c

@@ -122,7 +122,7 @@ struct pcr_hw_regs {
 #define XEC_CC_PCR_CLK32K_SRC_PIN	2
 #define XEC_CC_PCR_CLK32K_SRC_OFF	3
 
-#ifdef CONFIG_SOC_SERIES_MEC1501X
+#ifdef CONFIG_SOC_SERIES_MEC15XX
 #define XEC_CC_PCR3_CRYPTO_MASK		(BIT(26) | BIT(27) | BIT(28))
 #else
 #define XEC_CC_PCR3_CRYPTO_MASK		BIT(26)
@@ -263,7 +263,7 @@ static int periph_clk_src_using_pin(enum periph_clk32k_src src)
 	}
 }
 
-#ifdef CONFIG_SOC_SERIES_MEC1501X
+#ifdef CONFIG_SOC_SERIES_MEC15XX
 /* MEC15xx uses the same 32KHz source for both PLL and Peripheral 32K clock domains.
  * We ignore the peripheral clock source.
  * If XTAL is selected (parallel) or single-ended the external 32KHz MUST stay on
@@ -915,7 +915,7 @@ static inline int xec_clock_control_off(const struct device *dev,
  */
 static uint32_t get_turbo_clock(const struct device *dev)
 {
-#ifdef CONFIG_SOC_SERIES_MEC1501X
+#ifdef CONFIG_SOC_SERIES_MEC15XX
 	ARG_UNUSED(dev);
 
 	return MHZ(48);
@@ -1079,7 +1079,7 @@ const struct xec_pcr_config pcr_xec_config = {
 		(uint16_t)DT_INST_PROP_OR(0, pll_lock_timeout_ms, XEC_CC_DFLT_PLL_LOCK_WAIT_MS),
 	.period_min = (uint16_t)DT_INST_PROP_OR(0, clk32kmon_period_min, CNT32K_TMIN),
 	.period_max = (uint16_t)DT_INST_PROP_OR(0, clk32kmon_period_max, CNT32K_TMAX),
-	.core_clk_div = (uint8_t)DT_INST_PROP_OR(0, core_clk_div, CONFIG_SOC_MEC172X_PROC_CLK_DIV),
+	.core_clk_div = (uint8_t)DT_INST_PROP_OR(0, core_clk_div, CONFIG_SOC_MEC_PROC_CLK_DIV),
 	.xtal_se = (uint8_t)DT_INST_PROP_OR(0, xtal_single_ended, 0),
 	.max_dc_va = (uint8_t)DT_INST_PROP_OR(0, clk32kmon_duty_cycle_var_max, CNT32K_DUTY_MAX),
 	.min_valid = (uint8_t)DT_INST_PROP_OR(0, clk32kmon_valid_min, CNT32K_VAL_MIN),

drivers/espi/Kconfig.xec

@@ -39,7 +39,7 @@ config ESPI_PERIPHERAL_UART
 
 config ESPI_PERIPHERAL_UART_SOC_MAPPING
 	int "SoC port exposed as logical eSPI UART"
-	default 2 if SOC_SERIES_MEC1501X
+	default 2 if SOC_SERIES_MEC15XX
 	default 1 if SOC_SERIES_MEC172X
 	depends on ESPI_PERIPHERAL_UART
 	help
@@ -66,7 +66,7 @@ config ESPI_FLASH_BUFFER_SIZE
 config ESPI_SAF_XEC
 	bool "XEC Microchip ESPI SAF driver"
 	default y
-	depends on SOC_SERIES_MEC1501X
+	depends on SOC_SERIES_MEC15XX
 	depends on DT_HAS_MICROCHIP_XEC_ESPI_SAF_ENABLED
 	help
 	  Enable the Microchip XEC SAF ESPI driver for MEC15xx family.

drivers/led/led_mchp_xec.c

@@ -12,7 +12,7 @@
  */
 
 #include <soc.h>
-#ifndef CONFIG_SOC_SERIES_MEC1501X
+#ifndef CONFIG_SOC_SERIES_MEC15XX
 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
 #endif
@@ -207,7 +207,7 @@ static int xec_bbled_off(const struct device *dev, uint32_t led)
 	return 0;
 }
 
-#ifdef CONFIG_SOC_SERIES_MEC1501X
+#ifdef CONFIG_SOC_SERIES_MEC15XX
 static inline void xec_bbled_slp_en_clr(const struct device *dev)
 {
 	const struct xec_bbled_config * const cfg = dev->config;

drivers/timer/mchp_xec_rtos_timer.c

@@ -420,7 +420,7 @@ static int sys_clock_driver_init(void)
 			      | MCHP_BTMR_CTRL_COUNT_UP
 			      | (47UL << MCHP_BTMR_CTRL_PRESCALE_POS));
 
-#if CONFIG_SOC_SERIES_MEC1501X
+#if CONFIG_SOC_SERIES_MEC15XX
 	mchp_pcr_periph_slp_ctrl(PCR_B32TMR0, 0);
 #else
 	PCR_XEC_REGS->SLP_EN[BTMR32_0_PCR_REG_IDX] &= ~BIT(BTMR32_0_PCR_BITPOS);

samples/drivers/clock_control_xec/src/main.c

@@ -17,7 +17,7 @@ LOG_MODULE_REGISTER(clock32k, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
 
 #include <soc.h>
 
-#ifdef CONFIG_SOC_SERIES_MEC1501X
+#ifdef CONFIG_SOC_SERIES_MEC15XX
 static void pcr_clock_regs(void)
 {
 	struct pcr_regs *pcr = ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0));

soc/microchip/mec/Kconfig

@@ -22,7 +22,7 @@ if MCHP_MEC_UNSIGNED_HEADER
 
 config MCHP_MEC_HEADER_CHIP
 	string
-	default "mec152x" if SOC_SERIES_MEC1501X
+	default "mec15xx" if SOC_SERIES_MEC15XX
 	default "mec172x" if SOC_SERIES_MEC172X
 
 choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE
@@ -210,7 +210,7 @@ config MCHP_HEADER_VERBOSE_OUTPUT
 
 endif # MCHP_MEC_UNSIGNED_HEADER
 
-config SOC_MEC172X_PROC_CLK_DIV
+config SOC_MEC_PROC_CLK_DIV
 	int "PROC_CLK_DIV"
 	default 1
 	range 1 48

soc/microchip/mec/common/soc_i2c.c

@@ -32,7 +32,7 @@ struct mec_i2c_port {
  * TODO: MEC15xx and MEC172x handle ports with alternate pins.
  */
 static const struct mec_i2c_port mec_i2c_ports[] = {
-#if defined(CONFIG_SOC_SERIES_MEC172X) || defined(CONFIG_SOC_SERIES_MEC1501X)
+#if defined(CONFIG_SOC_SERIES_MEC172X) || defined(CONFIG_SOC_SERIES_MEC15XX)
 	{ 0004, 1, 0003, 1 },
 	{ 0131, 1, 0130, 1 }, /* VTR2. ALT on eSPI VTR3 {0073, 2, 0072, 2} */
 	{ 0155, 1, 0154, 1 },

soc/microchip/mec/common/spigen/mec_spi_gen.py

@@ -68,7 +68,7 @@ CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
              0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
 
 CHIP_DICT = {
-    'mec152x': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 },
+    'mec15xx': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 },
     'mec172x': { 'sram_base': 0xc0000, 'sram_size': 0x68000, 'header_ver': 3 },
 }
 
@@ -123,7 +123,7 @@ def build_header(chip, spi_config, hdr_spi_loc, pld_spi_loc, pld_entry_addr, pld
     """Build MEC152x/MEC172x Boot-ROM SPI image header
 
     Args:
-        chip: mec152x or mec172x
+        chip: mec15xx or mec172x
         spi_config: spi configuration
         hdr_spi_loc: Header location in SPI Image
         pld_spi_loc: Payload(FW binary) location in SPI Image
@@ -242,9 +242,9 @@ def parse_args():
     parser.add_argument("-c",
                         type=str,
                         dest="chip",
-                        choices = ["mec152x", "mec172x"],
+                        choices = ["mec15xx", "mec172x"],
                         default="mec172x",
-                        help="Chip name: mec172x(default) or mec152x")
+                        help="Chip name: mec172x(default) or mec15xx")
     parser.add_argument("-i",
                         type=str,
                         dest="infilename",

soc/microchip/mec/mec15xx/Kconfig

@@ -3,7 +3,7 @@
 # Copyright (c) 2018 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MEC1501X
+config SOC_SERIES_MEC15XX
 	select ARM
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
@@ -13,7 +13,7 @@ config SOC_SERIES_MEC1501X
 config SOC_MEC1501_HSZ
 	select HAS_MEC_HAL
 
-if SOC_SERIES_MEC1501X
+if SOC_SERIES_MEC15XX
 
 config RTOS_TIMER
 	bool "MEC1501 RTOS timer"
@@ -44,7 +44,7 @@ config SOC_MEC1501_VCI_PINS_AS_GPIOS
 choice
 	prompt "MEC1501 debug interface general configuration"
 	default SOC_MEC1501_DEBUG_WITHOUT_TRACING
-	depends on SOC_SERIES_MEC1501X
+	depends on SOC_SERIES_MEC15XX
 	help
 	  Select Debug SoC interface support for MEC15xx SoC family
 
@@ -98,4 +98,4 @@ config GPIO_INIT_PRIORITY
 
 endif # GPIO
 
-endif # SOC_SERIES_MEC1501X
+endif # SOC_SERIES_MEC15XX

soc/microchip/mec/mec15xx/Kconfig.defconfig.series

@@ -3,7 +3,7 @@
 # Copyright (c) 2018 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_MEC1501X
+if SOC_SERIES_MEC15XX
 
 config NUM_IRQS
 	# must be >= the highest interrupt number used
@@ -26,4 +26,4 @@ endif # RTOS_TIMER
 config CORTEX_M_SYSTICK
 	depends on !RTOS_TIMER
 
-endif # SOC_SERIES_MEC1501X
+endif # SOC_SERIES_MEC15XX

soc/microchip/mec/mec15xx/Kconfig.soc

@@ -3,18 +3,18 @@
 # Copyright (c) 2018 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_MEC1501X
+config SOC_SERIES_MEC15XX
 	bool
 	select SOC_FAMILY_MICROCHIP_MEC
 	help
 	  Enable support for Microchip MEC Cortex-M4 MCU series
 
 config SOC_SERIES
-	default "mec1501x" if SOC_SERIES_MEC1501X
+	default "mec15xx" if SOC_SERIES_MEC15XX
 
 config SOC_MEC1501_HSZ
 	bool
-	select SOC_SERIES_MEC1501X
+	select SOC_SERIES_MEC15XX
 
 config SOC
 	default "mec1501_hsz" if SOC_MEC1501_HSZ

soc/microchip/mec/soc.yml

@@ -1,7 +1,7 @@
 family:
 - name: microchip_mec
   series:
-  - name: mec1501x
+  - name: mec15xx
     socs:
     - name: mec1501_hsz
   - name: mec172x