soc: xilinx_zynq7000: Port to HWMv2

Ports the xilinx_zynq7000 SoC configuration to hardware model
version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/soc_legacy/arm/xilinx_zynq7000/Kconfig.soc

@@ -1,6 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-source "soc/soc_legacy/arm/xilinx_zynq7000/*/Kconfig.series"

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z010

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z010"
-	depends on SOC_XILINX_XC7Z010

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z015

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z015"
-	depends on SOC_XILINX_XC7Z015

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z030

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z030"
-	depends on SOC_XILINX_XC7Z030

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z035

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z035"
-	depends on SOC_XILINX_XC7Z035

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z045

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z045"
-	depends on SOC_XILINX_XC7Z045

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z100

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z100"
-	depends on SOC_XILINX_XC7Z100

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z007s

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z007S"
-	depends on SOC_XILINX_XC7Z007S

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z012s

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z012S"
-	depends on SOC_XILINX_XC7Z012S

soc/soc_legacy/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z014s

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config SOC
-	default "XC7Z014S"
-	depends on SOC_XILINX_XC7Z014S

soc/xilinx/zynq7000/Kconfig

@@ -3,6 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-config SOC
-	default "XC7Z020"
-	depends on SOC_XILINX_XC7Z020
+if SOC_FAMILY_XILINX_ZYNQ7000
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_XILINX_ZYNQ7000

soc/xilinx/zynq7000/Kconfig.defconfig

@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-source "soc/soc_legacy/arm/xilinx_zynq7000/*/Kconfig.defconfig.series"
+rsource "*/Kconfig.defconfig"
 
 if SOC_FAMILY_XILINX_ZYNQ7000
 

soc/xilinx/zynq7000/Kconfig.soc

@@ -6,12 +6,7 @@
 config SOC_FAMILY_XILINX_ZYNQ7000
 	bool
 
-if SOC_FAMILY_XILINX_ZYNQ7000
-
 config SOC_FAMILY
-	string
-	default "xilinx_zynq7000"
+	default "xilinx_zynq7000" if SOC_FAMILY_XILINX_ZYNQ7000
 
-source "soc/soc_legacy/arm/xilinx_zynq7000/*/Kconfig.soc"
-
-endif # SOC_FAMILY_XILINX_ZYNQ7000
+rsource "*/Kconfig.soc"

soc/xilinx/zynq7000/soc.yml

@@ -0,0 +1,18 @@
+family:
+- name: xilinx_zynq7000
+  series:
+  - name: xc7zxxx
+    socs:
+    - name: xc7z010
+    - name: xc7z010
+    - name: xc7z015
+    - name: xc7z020
+    - name: xc7z030
+    - name: xc7z035
+    - name: xc7z045
+    - name: xc7z100
+  - name: xc7zxxxs
+    socs:
+    - name: xc7z007s
+    - name: xc7z012s
+    - name: xc7z014s

soc/xilinx/zynq7000/xc7zxxx/CMakeLists.txt

@@ -5,4 +5,6 @@
 
 zephyr_sources(soc.c)
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

soc/xilinx/zynq7000/xc7zxxx/Kconfig

@@ -2,13 +2,11 @@
 # Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
 # SPDX-License-Identifier: Apache-2.0
 #
+# Device data: comp.
+# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
+#
 
 config SOC_SERIES_XILINX_XC7ZXXX
-	bool "Xilinx Zynq-7000 (XC7Zxxx) SoC series"
-	select SOC_FAMILY_XILINX_ZYNQ7000
 	select ARM
 	select CPU_CORTEX_A9
 	select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
-	help
-	  Enable support for the Xilinx Zynq-7000 (XC7Zxxx)
-	  SoC series (dual core ARM Cortex-A9).

soc/xilinx/zynq7000/xc7zxxx/Kconfig.defconfig

@@ -5,11 +5,6 @@
 
 if SOC_SERIES_XILINX_XC7ZXXX
 
-rsource "Kconfig.defconfig.xc7z*"
-
-config SOC_SERIES
-	default "xc7zxxx"
-
 # Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core
 config MP_MAX_NUM_CPUS
 	default 1

soc/xilinx/zynq7000/xc7zxxx/Kconfig.soc

@@ -6,55 +6,75 @@
 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
 #
 
-choice
-	prompt "XC7Zxxx SoC Selection"
-	depends on SOC_SERIES_XILINX_XC7ZXXX
+config SOC_SERIES_XILINX_XC7ZXXX
+	bool
+	select SOC_FAMILY_XILINX_ZYNQ7000
+	help
+	  Enable support for the Xilinx Zynq-7000 (XC7Zxxx)
+	  SoC series (dual core ARM Cortex-A9).
 
 config SOC_XILINX_XC7Z010
-	bool "XC7Z010"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXX
 	help
 	  2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
 	  28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
 
 config SOC_XILINX_XC7Z015
-	bool "XC7Z015"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXX
 	help
 	  2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
 	  74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
 	  up to 4 transceivers.
 
 config SOC_XILINX_XC7Z020
-	bool "XC7Z020"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXX
 	help
 	  2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
 	  85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
 
 config SOC_XILINX_XC7Z030
-	bool "XC7Z030"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXX
 	help
 	  2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
 	  125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
 	  up to 4 transceivers.
 
 config SOC_XILINX_XC7Z035
-	bool "XC7Z035"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXX
 	help
 	  2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
 	  275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
 	  up to 16 transceivers.
 
 config SOC_XILINX_XC7Z045
-	bool "XC7Z045"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXX
 	help
 	  2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
 	  350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
 	  up to 16 transceivers.
 
 config SOC_XILINX_XC7Z100
-	bool "XC7Z100"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXX
 	help
 	  2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
 	  444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
 	  up to 16 transceivers.
 
-endchoice
+config SOC_SERIES
+	default "xc7zxxx" if SOC_SERIES_XILINX_XC7ZXXX
+
+config SOC
+	default "xc7z010" if SOC_XILINX_XC7Z010
+	default "xc7z015" if SOC_XILINX_XC7Z015
+	default "xc7z020" if SOC_XILINX_XC7Z020
+	default "xc7z030" if SOC_XILINX_XC7Z030
+	default "xc7z035" if SOC_XILINX_XC7Z035
+	default "xc7z045" if SOC_XILINX_XC7Z045
+	default "xc7z100" if SOC_XILINX_XC7Z100

soc/xilinx/zynq7000/xc7zxxxs/CMakeLists.txt

@@ -5,4 +5,6 @@
 
 zephyr_sources(soc.c)
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

soc/xilinx/zynq7000/xc7zxxxs/Kconfig

@@ -2,13 +2,11 @@
 # Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
 # SPDX-License-Identifier: Apache-2.0
 #
+# Device data: comp.
+# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
+#
 
 config SOC_SERIES_XILINX_XC7ZXXXS
-	bool "Xilinx Zynq-7000S (XC7ZxxxS) SoC series"
-	select SOC_FAMILY_XILINX_ZYNQ7000
 	select ARM
 	select CPU_CORTEX_A9
 	select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
-	help
-	  Enable support for the Xilinx Zynq-7000S (XC7ZxxxS)
-	  SoC series (single core ARM Cortex-A9).

soc/xilinx/zynq7000/xc7zxxxs/Kconfig.defconfig

@@ -5,11 +5,6 @@
 
 if SOC_SERIES_XILINX_XC7ZXXXS
 
-rsource "Kconfig.defconfig.xc7z*"
-
-config SOC_SERIES
-	default "xc7zxxxs"
-
 config MP_MAX_NUM_CPUS
 	default 1
 

soc/xilinx/zynq7000/xc7zxxxs/Kconfig.soc

@@ -6,27 +6,39 @@
 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
 #
 
-choice
-	prompt "XC7ZxxxS SoC Selection"
-	depends on SOC_SERIES_XILINX_XC7ZXXXS
+config SOC_SERIES_XILINX_XC7ZXXXS
+	bool
+	select SOC_FAMILY_XILINX_ZYNQ7000
+	help
+	  Enable support for the Xilinx Zynq-7000S (XC7ZxxxS)
+	  SoC series (single core ARM Cortex-A9).
 
 config SOC_XILINX_XC7Z007S
-	bool "XC7Z007S"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXXS
 	help
 	  1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
 	  23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
 
 config SOC_XILINX_XC7Z012S
-	bool "XC7Z012S"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXXS
 	help
 	  1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
 	  55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
 	  up to 4 transceivers.
 
 config SOC_XILINX_XC7Z014S
-	bool "XC7Z014S"
+	bool
+	select SOC_SERIES_XILINX_XC7ZXXXS
 	help
 	  1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
 	  65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
 
-endchoice
+config SOC_SERIES
+	default "xc7zxxxs" if SOC_SERIES_XILINX_XC7ZXXXS
+
+config SOC
+	default "xc7z007s" if SOC_XILINX_XC7Z007S
+	default "xc7z012s" if SOC_XILINX_XC7Z012S
+	default "xc7z014s" if SOC_XILINX_XC7Z014S