diff --git a/soc/soc_legacy/riscv/litex_vexriscv/CMakeLists.txt b/soc/litex/litex_vexriscv/CMakeLists.txt
similarity index 60%
rename from soc/soc_legacy/riscv/litex_vexriscv/CMakeLists.txt
rename to soc/litex/litex_vexriscv/CMakeLists.txt
index 9cf7e86ab2b..3272d0359a1 100644
--- a/soc/soc_legacy/riscv/litex_vexriscv/CMakeLists.txt
+++ b/soc/litex/litex_vexriscv/CMakeLists.txt
@@ -5,8 +5,10 @@
 #
 
 zephyr_sources(
-    ${ZEPHYR_BASE}/soc/common/riscv/riscv-privileged/soc_irq.S
-    ${ZEPHYR_BASE}/soc/common/riscv/riscv-privileged/vector.S
+    ${ZEPHYR_BASE}/soc/common/riscv-privileged/soc_irq.S
+    ${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S
 )
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
diff --git a/soc/soc_legacy/riscv/litex_vexriscv/Kconfig.soc b/soc/litex/litex_vexriscv/Kconfig
similarity index 72%
rename from soc/soc_legacy/riscv/litex_vexriscv/Kconfig.soc
rename to soc/litex/litex_vexriscv/Kconfig
index a7e632e3afd..b13181f0177 100644
--- a/soc/soc_legacy/riscv/litex_vexriscv/Kconfig.soc
+++ b/soc/litex/litex_vexriscv/Kconfig
@@ -1,8 +1,7 @@
 # Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_RISCV32_LITEX_VEXRISCV
-	bool "LiteX VexRiscv system implementation"
+config SOC_LITEX_VEXRISCV
 	select RISCV
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
@@ -12,10 +11,10 @@ config SOC_RISCV32_LITEX_VEXRISCV
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 
-if SOC_RISCV32_LITEX_VEXRISCV
+if SOC_LITEX_VEXRISCV
 
 config LITEX_CSR_DATA_WIDTH
 	int "Select Control/Status register width"
 	default 32
 
-endif # SOC_RISCV32_LITEX_VEXRISCV
+endif # SOC_LITEX_VEXRISCV
diff --git a/soc/soc_legacy/riscv/litex_vexriscv/Kconfig.defconfig b/soc/litex/litex_vexriscv/Kconfig.defconfig
similarity index 63%
rename from soc/soc_legacy/riscv/litex_vexriscv/Kconfig.defconfig
rename to soc/litex/litex_vexriscv/Kconfig.defconfig
index 0088420459f..d2bb5c9ae73 100644
--- a/soc/soc_legacy/riscv/litex_vexriscv/Kconfig.defconfig
+++ b/soc/litex/litex_vexriscv/Kconfig.defconfig
@@ -1,10 +1,7 @@
 # Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_RISCV32_LITEX_VEXRISCV
-
-config SOC
-	default "litex_vexriscv"
+if SOC_LITEX_VEXRISCV
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 100000000
@@ -12,4 +9,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config NUM_IRQS
 	default 12
 
-endif # SOC_RISCV32_LITEX_VEXRISCV
+endif # SOC_LITEX_VEXRISCV
diff --git a/soc/litex/litex_vexriscv/Kconfig.soc b/soc/litex/litex_vexriscv/Kconfig.soc
new file mode 100644
index 00000000000..4c0c80717b4
--- /dev/null
+++ b/soc/litex/litex_vexriscv/Kconfig.soc
@@ -0,0 +1,10 @@
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_LITEX_VEXRISCV
+	bool
+	help
+	  LiteX VexRiscv system implementation
+
+config SOC
+	default "litex_vexriscv" if SOC_LITEX_VEXRISCV
diff --git a/soc/soc_legacy/riscv/litex_vexriscv/soc.h b/soc/litex/litex_vexriscv/soc.h
similarity index 100%
rename from soc/soc_legacy/riscv/litex_vexriscv/soc.h
rename to soc/litex/litex_vexriscv/soc.h
diff --git a/soc/litex/litex_vexriscv/soc.yml b/soc/litex/litex_vexriscv/soc.yml
new file mode 100644
index 00000000000..322f95a9e8d
--- /dev/null
+++ b/soc/litex/litex_vexriscv/soc.yml
@@ -0,0 +1,2 @@
+socs:
+- name: litex_vexriscv