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soc: nxp: lpc: Move wrong configurations

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Moves wrong configuration items to the correct files

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Jamie McCrae
2024-03-01 10:01:06 +00:00
committed by Carles Cufi
parent 8e02c08f96
commit dbc366c3c7
4 changed files with 43 additions and 43 deletions
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39
soc/nxp/lpc/lpc54xxx/Kconfig
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@@ -28,3 +28,42 @@ config SOC_LPC54114_M0
config MCUX_CORE_SUFFIX
default "_cm4" if SOC_LPC54114_M4
default "_cm0plus" if SOC_LPC54114_M0
if SOC_SERIES_LPC54XXX
config SECOND_CORE_MCUX
bool "LPC54114 Cortex-M0 second core"
help
Driver for second core startup
config SECOND_CORE_BOOT_ADDRESS_MCUX
depends on SECOND_CORE_MCUX
hex "Address the second core will boot at"
default 0x20010000
help
This is the address the second core will boot from. Additionally this
address is where we will copy the SECOND_IMAGE to. We default this to
the base of SRAM1.
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
# Move the LMA address of second core into flash
config BUILD_OUTPUT_ADJUST_LMA
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
default "-0x20010000+\
$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))"
config BUILD_OUTPUT_INFO_HEADER
default y
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
config LPC54XXX_SRAM2_CLOCK
bool "Clock LPC54XXX SRAM2"
default y
help
SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
will enable the clock to this RAM bank. Disable this Kconfig to leave
this ram bank untouched out of reset.
endif # SOC_SERIES_LPC54XXX

39
soc/nxp/lpc/lpc54xxx/Kconfig.soc
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@@ -36,42 +36,3 @@ config SOC_PART_NUMBER_LPC54114J256BD64
config SOC_PART_NUMBER
default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64
if SOC_SERIES_LPC54XXX
config SECOND_CORE_MCUX
bool "LPC54114 Cortex-M0 second core"
help
Driver for second core startup
config SECOND_CORE_BOOT_ADDRESS_MCUX
depends on SECOND_CORE_MCUX
hex "Address the second core will boot at"
default 0x20010000
help
This is the address the second core will boot from. Additionally this
address is where we will copy the SECOND_IMAGE to. We default this to
the base of SRAM1.
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
# Move the LMA address of second core into flash
config BUILD_OUTPUT_ADJUST_LMA
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
default "-0x20010000+\
$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))"
config BUILD_OUTPUT_INFO_HEADER
default y
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
config LPC54XXX_SRAM2_CLOCK
bool "Clock LPC54XXX SRAM2"
default y
help
SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
will enable the clock to this RAM bank. Disable this Kconfig to leave
this ram bank untouched out of reset.
endif # SOC_SERIES_LPC54XXX

4
soc/nxp/lpc/lpc55xxx/Kconfig
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@@ -107,4 +107,8 @@ config SOC_FLASH_MCUX
endif # SOC_LPC55S69
config MCUX_CORE_SUFFIX
default "_cm33_core0" if SOC_LPC55S69_CPU0
default "_cm33_core1" if SOC_LPC55S69_CPU1
endif # SOC_SERIES_LPC55XXX

4
soc/nxp/lpc/lpc55xxx/Kconfig.soc
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@@ -36,10 +36,6 @@ config SOC_LPC55S69_CPU1
bool
select SOC_LPC55S69
config MCUX_CORE_SUFFIX
default "_cm33_core0" if SOC_LPC55S69_CPU0
default "_cm33_core1" if SOC_LPC55S69_CPU1
config SOC
default "lpc55s69" if SOC_LPC55S69_CPU0 || SOC_LPC55S69_CPU1
default "lpc55s06" if SOC_LPC55S06