michael/zephyr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch: xtensa: clean up interrupt handling

Browse Source 
Simplifying flow of handling interrupts:
- removing all _soc_inthandlers.h
- removing xtensa_intgen*
- removing XTENSA_GEN_HANDLERS Kconfig
- keeping optimized irq detection
- single handler with irq level as parameter

Signed-off-by: Maciej Kusio <rysiof@gmail.com>
This commit is contained in:
Maciej Kusio
2025-09-05 14:35:35 -07:00
committed by Henrik Brix Andersen
parent 885329cc1d
commit df40dff6fb
22 changed files with 124 additions and 3249 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/xtensa/Kconfig
View File

@@ -22,16 +22,6 @@ config XTENSA_RESET_VECTOR
This is always needed for the simulator. Real boards may already
implement this in boot ROM.
config XTENSA_GEN_HANDLERS
bool "Automatically generate interrupt handlers"
default n
help
When set, an "xtensa_handlers.h" file is generated
containing definitions for the interrupt entry code of the
target Xtensa core, based automatically on the details in
the core-isa.h file. This replaces the previous scheme
where a _soc_inthandlers.h file would be generated offline.
config XTENSA_USE_CORE_CRT1
bool "Use crt1.S from core"
default y

19
arch/xtensa/core/CMakeLists.txt
View File

@@ -108,25 +108,6 @@ add_dependencies(zephyr_interface zsr_h)
unset(MAY_NEED_SYSCALL_SCRATCH_REG)
# Similar: auto-generate interrupt handlers
set(HANDLERS ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_handlers)
add_custom_command(
OUTPUT ${HANDLERS}_tmp.c
COMMAND ${CMAKE_C_COMPILER} -E -U__XCC__
${XTENSA_CONFIG_HAL_INCLUDE_DIR}
-o ${HANDLERS}_tmp.c
- < ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.tmpl)
add_custom_command(
OUTPUT ${HANDLERS}.h
DEPENDS ${HANDLERS}_tmp.c
COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.py
${HANDLERS}_tmp.c > ${HANDLERS}.h)
add_custom_target(xtensa_handlers_h DEPENDS ${HANDLERS}.h)
add_dependencies(zephyr_interface xtensa_handlers_h)
# Auto-generate interrupt vector entry
set(VECS_LD ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_vectors.ld)
add_custom_command(OUTPUT ${VECS_LD} DEPENDS ${CORE_ISA_DM}

245
arch/xtensa/core/vector_handlers.c
View File

@@ -15,12 +15,6 @@
#include <zephyr/zsr.h>
#include <zephyr/arch/common/exc_handle.h>
#ifdef CONFIG_XTENSA_GEN_HANDLERS
#include <xtensa_handlers.h>
#else
#include <_soc_inthandlers.h>
#endif
#include <kernel_internal.h>
#include <xtensa_internal.h>
#include <xtensa_stack.h>
@@ -370,123 +364,36 @@ void arch_ipi_lazy_coprocessors_save(void)
#endif
}
/* The wrapper code lives here instead of in the python script that
* generates _xtensa_handle_one_int*(). Seems cleaner, still kind of
* ugly.
*
* This may be unused depending on number of interrupt levels
* supported by the SoC.
*/
#if XCHAL_NUM_INTERRUPTS <= 32
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \
return return_to(interrupted_stack); \
}
#endif /* XCHAL_NUM_INTERRUPTS <= 32 */
#if XCHAL_NUM_INTERRUPTS > 32 && XCHAL_NUM_INTERRUPTS <= 64
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(1, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
} \
return return_to(interrupted_stack); \
}
#endif /* XCHAL_NUM_INTERRUPTS > 32 && XCHAL_NUM_INTERRUPTS <= 64 */
#if XCHAL_NUM_INTERRUPTS > 64 && XCHAL_NUM_INTERRUPTS <= 96
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(1, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable2 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(2, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear2 %0" : : "r"(m)); \
} \
return return_to(interrupted_stack); \
}
#endif /* XCHAL_NUM_INTERRUPTS > 64 && XCHAL_NUM_INTERRUPTS <= 96 */
#if XCHAL_NUM_INTERRUPTS > 96
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(1, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable2 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(2, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear2 %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt3 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable3 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(3, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear3 %0" : : "r"(m)); \
} \
return return_to(interrupted_stack); \
}
#endif /* XCHAL_NUM_INTERRUPTS > 96 */
#define DECLARE_IRQ(lvl) \
{ \
XCHAL_INTLEVEL##lvl##_MASK, \
}
#elif XCHAL_NUM_INTERRUPTS <= 64
#define DECLARE_IRQ(lvl) \
{ \
XCHAL_INTLEVEL##lvl##_MASK, \
XCHAL_INTLEVEL##lvl##_MASK1, \
}
#elif XCHAL_NUM_INTERRUPTS <= 96
#define DECLARE_IRQ(lvl) \
{ \
XCHAL_INTLEVEL##lvl##_MASK, \
XCHAL_INTLEVEL##lvl##_MASK1, \
XCHAL_INTLEVEL##lvl##_MASK2, \
}
#elif XCHAL_NUM_INTERRUPTS <= 128
#define DECLARE_IRQ(lvl) \
{ \
XCHAL_INTLEVEL##lvl##_MASK, \
XCHAL_INTLEVEL##lvl##_MASK1, \
XCHAL_INTLEVEL##lvl##_MASK2, \
XCHAL_INTLEVEL##lvl##_MASK3, \
}
#else
#error "xtensa supports up to 128 interrupts"
#endif
#if XCHAL_HAVE_NMI
#define MAX_INTR_LEVEL XCHAL_NMILEVEL
@@ -497,6 +404,102 @@ __unused void *xtensa_int##l##_c(void *interrupted_stack) \
#define MAX_INTR_LEVEL 0
#endif
#define GRP_COUNT (ROUND_UP(XCHAL_NUM_INTERRUPTS, 32) / 32)
static const uint32_t xtensa_lvl_mask[MAX_INTR_LEVEL][GRP_COUNT] = {
#if MAX_INTR_LEVEL >= 1
DECLARE_IRQ(1),
#endif
#if MAX_INTR_LEVEL >= 2
DECLARE_IRQ(2),
#endif
#if MAX_INTR_LEVEL >= 3
DECLARE_IRQ(3),
#endif
#if MAX_INTR_LEVEL >= 4
DECLARE_IRQ(4),
#endif
#if MAX_INTR_LEVEL >= 5
DECLARE_IRQ(5),
#endif
#if MAX_INTR_LEVEL >= 6
DECLARE_IRQ(6),
#endif
#if MAX_INTR_LEVEL >= 7
DECLARE_IRQ(7),
#endif
};
/* Handles all interrupts for given IRQ Level.
* - Supports up to 128 interrupts (max supported by Xtensa)
* - Supports all IRQ levels
* - Uses __builtin_ctz that for most xtensa configurations will be optimized using nsau instruction
*/
__unused static void xtensa_handle_irq_lvl(int irq_lvl)
{
int irq;
uint32_t irq_mask;
uint32_t intenable;
#if XCHAL_NUM_INTERRUPTS > 0
__asm__ volatile("rsr.interrupt %0" : "=r"(irq_mask));
__asm__ volatile("rsr.intenable %0" : "=r"(intenable));
irq_mask &= intenable;
irq_mask &= xtensa_lvl_mask[irq_lvl - 1][0];
while (irq_mask) {
irq = __builtin_ctz(irq_mask);
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
__asm__ volatile("wsr.intclear %0" : : "r"(BIT(irq)));
irq_mask ^= BIT(irq);
}
#endif
#if XCHAL_NUM_INTERRUPTS > 32
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irq_mask));
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable));
irq_mask &= intenable;
irq_mask &= xtensa_lvl_mask[irq_lvl - 1][1];
while (irq_mask) {
irq = __builtin_ctz(irq_mask);
_sw_isr_table[irq + 32].isr(_sw_isr_table[irq + 32].arg);
__asm__ volatile("wsr.intclear1 %0" : : "r"(BIT(irq)));
irq_mask ^= BIT(irq);
}
#endif
#if XCHAL_NUM_INTERRUPTS > 64
__asm__ volatile("rsr.interrupt2 %0" : "=r"(irq_mask));
__asm__ volatile("rsr.intenable2 %0" : "=r"(intenable2));
irq_mask &= intenable;
irq_mask &= xtensa_lvl_mask[irq_lvl - 1][2];
while (irq_mask) {
irq = __builtin_ctz(irq_mask);
_sw_isr_table[irq + 64].isr(_sw_isr_table[irq + 64].arg);
__asm__ volatile("wsr.intclear2 %0" : : "r"(BIT(irq)));
irq_mask ^= BIT(irq);
}
#endif
#if XCHAL_NUM_INTERRUPTS > 96
__asm__ volatile("rsr.interrupt3 %0" : "=r"(irq_mask));
__asm__ volatile("rsr.intenable3 %0" : "=r"(intenable));
irq_mask &= intenable;
irq_mask &= xtensa_lvl_mask[irq_lvl - 1][3];
while (irq_mask) {
irq = __builtin_ctz(irq_mask);
_sw_isr_table[irq + 96].isr(_sw_isr_table[irq + 96].arg);
__asm__ volatile("wsr.intclear3 %0" : : "r"(BIT(irq)));
irq_mask ^= BIT(irq);
}
#endif
}
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
usage_stop(); \
xtensa_handle_irq_lvl(l); \
return return_to(interrupted_stack); \
}
#if MAX_INTR_LEVEL >= 2
DEF_INT_C_HANDLER(2)
#endif

142
arch/xtensa/core/xtensa_intgen.py
View File

@@ -1,142 +0,0 @@
#!/usr/bin/env python3
import re
import fileinput
# Pass an Xtensa core-isa.h file on stdin or the command line, emits a
# C file on output containing optimized interrupt dispatch routines.
# FIXME: looking at the assembly generated by the ESP-32 toolchain,
# this isn't as optimal as I'd hoped. the individual cases are tested
# using a L32R + BNONE (i.e. a full mask test) instead of a BBSI, and
# the handlers are being invoked with CALL8 instead of CALL4,
# inexplicably wasting four words of stack. Maybe this should be
# emitting assembly instead. Wouldn't be much more complicated and
# would share all the same structure.
# My manual count of instructions says that a linear search becomes
# faster on average when there are three or fewer bits to test. Would
# be four, if the compiler would generate BBSI instructions.
MAX_TESTS = 3
ints_by_lvl = {}
# print() wrapper that automatically handles indentation levels
cindent = 0
def cprint(s):
global cindent
if s.endswith(":"):
print(s)
return
if s.find("}") >= 0:
cindent -= 1
s = cindent*"\t" + s
print(s)
if s.find("{") >= 0:
cindent += 1
def emit_int_handler(ints):
if len(ints) <= MAX_TESTS:
for i in ints:
# FIXME: a little work could allow us to extract the
# handler pointer and argument as literals, saving a few
# instructions and avoiding the need to link in
# _sw_isr_table entirely.
cprint("if (mask & BIT(%d)) {" % i)
cprint("mask = BIT(%d);" % i)
cprint("irq = %d;" % i)
cprint("goto handle_irq;")
cprint("}")
else:
half = int(len(ints)/2)
m = 0
for i in ints[0:half]:
m |= 1 << i
cprint("if (mask & " + ("0x%x" % (m)) + ") {")
emit_int_handler(ints[0:half])
cprint("} else {")
emit_int_handler(ints[half:])
cprint("}")
########################################################################
# Annoyingly need to join lines and remove #-marked annotations. Some
# versions of the preprocessor (ahem, esp32 SDK) like to include
# newlines in the output where the original expressions are expanded
# from 100% single line macros. Slurp it into a single string and
# parse via whitespace.
blob = ""
for l in fileinput.input():
l = l if l.find("#") < 0 else l[0:l.find("#")]
blob += l.rstrip() + " "
for match in re.finditer(r'__xtensa_int_level_magic__\s+(\d+)\s+(\d+)', blob):
irq = int(match.group(1))
lvl = int(match.group(2))
if lvl not in ints_by_lvl:
ints_by_lvl[lvl] = []
ints_by_lvl[lvl].append(irq)
cprint("/*")
cprint(" * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.")
cprint(" *")
cprint(" * Functions here are designed to produce efficient code to")
cprint(" * search an Xtensa bitmask of interrupts, inspecting only those bits")
cprint(" * declared to be associated with a given interrupt level. Each")
cprint(" * dispatcher will handle exactly one flagged interrupt, in numerical")
cprint(" * order (low bits first) and will return a mask of that bit that can")
cprint(" * then be cleared by the calling code. Unrecognized bits for the")
cprint(" * level will invoke an error handler.")
cprint(" */")
cprint("")
# Re-include the core-isa header and be sure our definitions match, for sanity
cprint("#include <xtensa/config/core-isa.h>")
cprint("#include <zephyr/sys/util.h>")
cprint("#include <zephyr/sw_isr_table.h>")
cprint("")
for l in ints_by_lvl:
for i in ints_by_lvl[l]:
v = "XCHAL_INT" + str(i) + "_LEVEL"
cprint("#if !defined(" + v + ") || " + str(v) + " != " + str(l))
cprint("#error core-isa.h interrupt level does not match dispatcher!")
cprint("#endif")
cprint("")
# Populate all theoretical levels just in case. Odd cores have been
# seen in the wild with "empty" interrupt levels that exist in the
# hardware but without any interrupts associated with them. The
# unused handlers will be ignored if uncalled.
max = 15
for lvl in range(0, max+1):
if not lvl in ints_by_lvl:
ints_by_lvl[lvl] = []
# Emit the handlers
for lvl in ints_by_lvl:
cprint("static inline int _xtensa_handle_one_int" +
str(lvl) + "(unsigned int set, unsigned int mask)")
cprint("{")
if not ints_by_lvl[lvl]:
cprint("return 0;")
cprint("}")
continue
cprint("int irq;")
print("")
if int(len(ints_by_lvl[lvl])) > 32:
emit_int_handler((sorted(ints_by_lvl[lvl]))[0:31])
else:
emit_int_handler(sorted(ints_by_lvl[lvl]))
cprint("return 0;")
cprint("handle_irq:")
cprint("_sw_isr_table[set * 32 + irq].isr(_sw_isr_table[set * 32 + irq].arg);")
cprint("return mask;")
cprint("}")
cprint("")

139
arch/xtensa/core/xtensa_intgen.tmpl
View File

@@ -1,139 +0,0 @@
#include <xtensa/config/core-isa.h>
/*
* Not a C source code file.
*
* Intended to be preprocessed only, to produce output for
* interpretation by the xtensa-int-handlers.py script. Literally all
* this does is emit records for which interrupts are at which level,
* available per-hardware by an SDK-provided core-isa.h file.
*/
__xtensa_int_level_magic__ 0 XCHAL_INT0_LEVEL
__xtensa_int_level_magic__ 1 XCHAL_INT1_LEVEL
__xtensa_int_level_magic__ 2 XCHAL_INT2_LEVEL
__xtensa_int_level_magic__ 3 XCHAL_INT3_LEVEL
__xtensa_int_level_magic__ 4 XCHAL_INT4_LEVEL
__xtensa_int_level_magic__ 5 XCHAL_INT5_LEVEL
__xtensa_int_level_magic__ 6 XCHAL_INT6_LEVEL
__xtensa_int_level_magic__ 7 XCHAL_INT7_LEVEL
__xtensa_int_level_magic__ 8 XCHAL_INT8_LEVEL
__xtensa_int_level_magic__ 9 XCHAL_INT9_LEVEL
__xtensa_int_level_magic__ 10 XCHAL_INT10_LEVEL
__xtensa_int_level_magic__ 11 XCHAL_INT11_LEVEL
__xtensa_int_level_magic__ 12 XCHAL_INT12_LEVEL
__xtensa_int_level_magic__ 13 XCHAL_INT13_LEVEL
__xtensa_int_level_magic__ 14 XCHAL_INT14_LEVEL
__xtensa_int_level_magic__ 15 XCHAL_INT15_LEVEL
__xtensa_int_level_magic__ 16 XCHAL_INT16_LEVEL
__xtensa_int_level_magic__ 17 XCHAL_INT17_LEVEL
__xtensa_int_level_magic__ 18 XCHAL_INT18_LEVEL
__xtensa_int_level_magic__ 19 XCHAL_INT19_LEVEL
__xtensa_int_level_magic__ 20 XCHAL_INT20_LEVEL
__xtensa_int_level_magic__ 21 XCHAL_INT21_LEVEL
__xtensa_int_level_magic__ 22 XCHAL_INT22_LEVEL
__xtensa_int_level_magic__ 23 XCHAL_INT23_LEVEL
__xtensa_int_level_magic__ 24 XCHAL_INT24_LEVEL
__xtensa_int_level_magic__ 25 XCHAL_INT25_LEVEL
__xtensa_int_level_magic__ 26 XCHAL_INT26_LEVEL
__xtensa_int_level_magic__ 27 XCHAL_INT27_LEVEL
__xtensa_int_level_magic__ 28 XCHAL_INT28_LEVEL
__xtensa_int_level_magic__ 29 XCHAL_INT29_LEVEL
__xtensa_int_level_magic__ 30 XCHAL_INT30_LEVEL
__xtensa_int_level_magic__ 31 XCHAL_INT31_LEVEL
__xtensa_int_level_magic__ 32 XCHAL_INT32_LEVEL
__xtensa_int_level_magic__ 33 XCHAL_INT33_LEVEL
__xtensa_int_level_magic__ 34 XCHAL_INT34_LEVEL
__xtensa_int_level_magic__ 35 XCHAL_INT35_LEVEL
__xtensa_int_level_magic__ 36 XCHAL_INT36_LEVEL
__xtensa_int_level_magic__ 37 XCHAL_INT37_LEVEL
__xtensa_int_level_magic__ 38 XCHAL_INT38_LEVEL
__xtensa_int_level_magic__ 39 XCHAL_INT39_LEVEL
__xtensa_int_level_magic__ 40 XCHAL_INT40_LEVEL
__xtensa_int_level_magic__ 41 XCHAL_INT41_LEVEL
__xtensa_int_level_magic__ 42 XCHAL_INT42_LEVEL
__xtensa_int_level_magic__ 43 XCHAL_INT43_LEVEL
__xtensa_int_level_magic__ 44 XCHAL_INT44_LEVEL
__xtensa_int_level_magic__ 45 XCHAL_INT45_LEVEL
__xtensa_int_level_magic__ 46 XCHAL_INT46_LEVEL
__xtensa_int_level_magic__ 47 XCHAL_INT47_LEVEL
__xtensa_int_level_magic__ 48 XCHAL_INT48_LEVEL
__xtensa_int_level_magic__ 49 XCHAL_INT49_LEVEL
__xtensa_int_level_magic__ 50 XCHAL_INT50_LEVEL
__xtensa_int_level_magic__ 51 XCHAL_INT51_LEVEL
__xtensa_int_level_magic__ 52 XCHAL_INT52_LEVEL
__xtensa_int_level_magic__ 53 XCHAL_INT53_LEVEL
__xtensa_int_level_magic__ 54 XCHAL_INT54_LEVEL
__xtensa_int_level_magic__ 55 XCHAL_INT55_LEVEL
__xtensa_int_level_magic__ 56 XCHAL_INT56_LEVEL
__xtensa_int_level_magic__ 57 XCHAL_INT57_LEVEL
__xtensa_int_level_magic__ 58 XCHAL_INT58_LEVEL
__xtensa_int_level_magic__ 59 XCHAL_INT59_LEVEL
__xtensa_int_level_magic__ 60 XCHAL_INT60_LEVEL
__xtensa_int_level_magic__ 61 XCHAL_INT61_LEVEL
__xtensa_int_level_magic__ 62 XCHAL_INT62_LEVEL
__xtensa_int_level_magic__ 63 XCHAL_INT63_LEVEL
__xtensa_int_level_magic__ 64 XCHAL_INT64_LEVEL
__xtensa_int_level_magic__ 65 XCHAL_INT65_LEVEL
__xtensa_int_level_magic__ 66 XCHAL_INT66_LEVEL
__xtensa_int_level_magic__ 67 XCHAL_INT67_LEVEL
__xtensa_int_level_magic__ 68 XCHAL_INT68_LEVEL
__xtensa_int_level_magic__ 69 XCHAL_INT69_LEVEL
__xtensa_int_level_magic__ 70 XCHAL_INT70_LEVEL
__xtensa_int_level_magic__ 71 XCHAL_INT71_LEVEL
__xtensa_int_level_magic__ 72 XCHAL_INT72_LEVEL
__xtensa_int_level_magic__ 73 XCHAL_INT73_LEVEL
__xtensa_int_level_magic__ 74 XCHAL_INT74_LEVEL
__xtensa_int_level_magic__ 75 XCHAL_INT75_LEVEL
__xtensa_int_level_magic__ 76 XCHAL_INT76_LEVEL
__xtensa_int_level_magic__ 77 XCHAL_INT77_LEVEL
__xtensa_int_level_magic__ 78 XCHAL_INT78_LEVEL
__xtensa_int_level_magic__ 79 XCHAL_INT79_LEVEL
__xtensa_int_level_magic__ 80 XCHAL_INT80_LEVEL
__xtensa_int_level_magic__ 81 XCHAL_INT81_LEVEL
__xtensa_int_level_magic__ 82 XCHAL_INT82_LEVEL
__xtensa_int_level_magic__ 83 XCHAL_INT83_LEVEL
__xtensa_int_level_magic__ 84 XCHAL_INT84_LEVEL
__xtensa_int_level_magic__ 85 XCHAL_INT85_LEVEL
__xtensa_int_level_magic__ 86 XCHAL_INT86_LEVEL
__xtensa_int_level_magic__ 87 XCHAL_INT87_LEVEL
__xtensa_int_level_magic__ 88 XCHAL_INT88_LEVEL
__xtensa_int_level_magic__ 89 XCHAL_INT89_LEVEL
__xtensa_int_level_magic__ 90 XCHAL_INT90_LEVEL
__xtensa_int_level_magic__ 91 XCHAL_INT91_LEVEL
__xtensa_int_level_magic__ 92 XCHAL_INT92_LEVEL
__xtensa_int_level_magic__ 93 XCHAL_INT93_LEVEL
__xtensa_int_level_magic__ 94 XCHAL_INT94_LEVEL
__xtensa_int_level_magic__ 95 XCHAL_INT95_LEVEL
__xtensa_int_level_magic__ 96 XCHAL_INT96_LEVEL
__xtensa_int_level_magic__ 97 XCHAL_INT97_LEVEL
__xtensa_int_level_magic__ 98 XCHAL_INT98_LEVEL
__xtensa_int_level_magic__ 99 XCHAL_INT99_LEVEL
__xtensa_int_level_magic__ 100 XCHAL_INT100_LEVEL
__xtensa_int_level_magic__ 101 XCHAL_INT101_LEVEL
__xtensa_int_level_magic__ 102 XCHAL_INT102_LEVEL
__xtensa_int_level_magic__ 103 XCHAL_INT103_LEVEL
__xtensa_int_level_magic__ 104 XCHAL_INT104_LEVEL
__xtensa_int_level_magic__ 105 XCHAL_INT105_LEVEL
__xtensa_int_level_magic__ 106 XCHAL_INT106_LEVEL
__xtensa_int_level_magic__ 107 XCHAL_INT107_LEVEL
__xtensa_int_level_magic__ 108 XCHAL_INT108_LEVEL
__xtensa_int_level_magic__ 109 XCHAL_INT109_LEVEL
__xtensa_int_level_magic__ 110 XCHAL_INT110_LEVEL
__xtensa_int_level_magic__ 111 XCHAL_INT111_LEVEL
__xtensa_int_level_magic__ 112 XCHAL_INT112_LEVEL
__xtensa_int_level_magic__ 113 XCHAL_INT113_LEVEL
__xtensa_int_level_magic__ 114 XCHAL_INT114_LEVEL
__xtensa_int_level_magic__ 115 XCHAL_INT115_LEVEL
__xtensa_int_level_magic__ 116 XCHAL_INT116_LEVEL
__xtensa_int_level_magic__ 117 XCHAL_INT117_LEVEL
__xtensa_int_level_magic__ 118 XCHAL_INT118_LEVEL
__xtensa_int_level_magic__ 119 XCHAL_INT119_LEVEL
__xtensa_int_level_magic__ 120 XCHAL_INT120_LEVEL
__xtensa_int_level_magic__ 121 XCHAL_INT121_LEVEL
__xtensa_int_level_magic__ 122 XCHAL_INT122_LEVEL
__xtensa_int_level_magic__ 123 XCHAL_INT123_LEVEL
__xtensa_int_level_magic__ 124 XCHAL_INT124_LEVEL
__xtensa_int_level_magic__ 125 XCHAL_INT125_LEVEL
__xtensa_int_level_magic__ 126 XCHAL_INT126_LEVEL
__xtensa_int_level_magic__ 127 XCHAL_INT127_LEVEL

1
soc/amd/acp_6_0/Kconfig
View File

@@ -2,7 +2,6 @@
# SPDX-License-Identifier: Apache-2.0
config SOC_ACP_6_0
select XTENSA
select XTENSA_GEN_HANDLERS
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
select XTENSA_RESET_VECTOR
select ATOMIC_OPERATIONS_BUILTIN

3
soc/cdns/dc233c/Kconfig.defconfig
View File

@@ -6,9 +6,6 @@
if SOC_XTENSA_DC233C
config SOC_XTENSA_DC233C
select XTENSA_GEN_HANDLERS
config XTENSA_MMU_NUM_L2_TABLES
int
default 48 if XTENSA_MMU

296
soc/cdns/sample_controller32/include/_soc_inthandlers.h
View File

@@ -1,296 +0,0 @@
/*
* Copyright (c) 2024 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x7f) {
if (mask & 0x7) {
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
} else {
if (mask & 0x18) {
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
} else {
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
}
}
} else {
if (mask & 0x38080) {
if (mask & 0x8080) {
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
if (mask & BIT(15)) {
mask = BIT(15);
irq = 15;
goto handle_irq;
}
} else {
if (mask & BIT(16)) {
mask = BIT(16);
irq = 16;
goto handle_irq;
}
if (mask & BIT(17)) {
mask = BIT(17);
irq = 17;
goto handle_irq;
}
}
} else {
if (mask & 0xc0000) {
if (mask & BIT(18)) {
mask = BIT(18);
irq = 18;
goto handle_irq;
}
if (mask & BIT(19)) {
mask = BIT(19);
irq = 19;
goto handle_irq;
}
} else {
if (mask & BIT(20)) {
mask = BIT(20);
irq = 20;
goto handle_irq;
}
if (mask & BIT(22)) {
mask = BIT(22);
irq = 22;
goto handle_irq;
}
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x600) {
if (mask & BIT(9)) {
mask = BIT(9);
irq = 9;
goto handle_irq;
}
if (mask & BIT(10)) {
mask = BIT(10);
irq = 10;
goto handle_irq;
}
} else {
if (mask & BIT(11)) {
mask = BIT(11);
irq = 11;
goto handle_irq;
}
if (mask & BIT(21)) {
mask = BIT(21);
irq = 21;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(12)) {
mask = BIT(12);
irq = 12;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(13)) {
mask = BIT(13);
irq = 13;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(14)) {
mask = BIT(14);
irq = 14;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}

271
soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h
View File

@@ -1,271 +0,0 @@
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
if (mask & 0x7f) {
if (mask & 0x7) {
if (mask & (1 << 0)) {
const struct _isr_table_entry *e = &_sw_isr_table[0];
e->isr(e->arg);
return 1 << 0;
}
if (mask & (1 << 1)) {
const struct _isr_table_entry *e = &_sw_isr_table[1];
e->isr(e->arg);
return 1 << 1;
}
if (mask & (1 << 2)) {
const struct _isr_table_entry *e = &_sw_isr_table[2];
e->isr(e->arg);
return 1 << 2;
}
} else {
if (mask & 0x18) {
if (mask & (1 << 3)) {
const struct _isr_table_entry *e = &_sw_isr_table[3];
e->isr(e->arg);
return 1 << 3;
}
if (mask & (1 << 4)) {
const struct _isr_table_entry *e = &_sw_isr_table[4];
e->isr(e->arg);
return 1 << 4;
}
} else {
if (mask & (1 << 5)) {
const struct _isr_table_entry *e = &_sw_isr_table[5];
e->isr(e->arg);
return 1 << 5;
}
if (mask & (1 << 6)) {
const struct _isr_table_entry *e = &_sw_isr_table[6];
e->isr(e->arg);
return 1 << 6;
}
}
}
} else {
if (mask & 0x18080) {
if (mask & (1 << 7)) {
const struct _isr_table_entry *e = &_sw_isr_table[7];
e->isr(e->arg);
return 1 << 7;
}
if (mask & (1 << 15)) {
const struct _isr_table_entry *e = &_sw_isr_table[15];
e->isr(e->arg);
return 1 << 15;
}
if (mask & (1 << 16)) {
const struct _isr_table_entry *e = &_sw_isr_table[16];
e->isr(e->arg);
return 1 << 16;
}
} else {
if (mask & 0x60000) {
if (mask & (1 << 17)) {
const struct _isr_table_entry *e = &_sw_isr_table[17];
e->isr(e->arg);
return 1 << 17;
}
if (mask & (1 << 18)) {
const struct _isr_table_entry *e = &_sw_isr_table[18];
e->isr(e->arg);
return 1 << 18;
}
} else {
if (mask & (1 << 19)) {
const struct _isr_table_entry *e = &_sw_isr_table[19];
e->isr(e->arg);
return 1 << 19;
}
if (mask & (1 << 20)) {
const struct _isr_table_entry *e = &_sw_isr_table[20];
e->isr(e->arg);
return 1 << 20;
}
}
}
}
return 0;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
if (mask & (1 << 8)) {
const struct _isr_table_entry *e = &_sw_isr_table[8];
e->isr(e->arg);
return 1 << 8;
}
return 0;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
if (mask & 0x600) {
if (mask & (1 << 9)) {
const struct _isr_table_entry *e = &_sw_isr_table[9];
e->isr(e->arg);
return 1 << 9;
}
if (mask & (1 << 10)) {
const struct _isr_table_entry *e = &_sw_isr_table[10];
e->isr(e->arg);
return 1 << 10;
}
} else {
if (mask & (1 << 11)) {
const struct _isr_table_entry *e = &_sw_isr_table[11];
e->isr(e->arg);
return 1 << 11;
}
if (mask & (1 << 21)) {
const struct _isr_table_entry *e = &_sw_isr_table[21];
e->isr(e->arg);
return 1 << 21;
}
}
return 0;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
if (mask & (1 << 12)) {
const struct _isr_table_entry *e = &_sw_isr_table[12];
e->isr(e->arg);
return 1 << 12;
}
return 0;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
if (mask & (1 << 13)) {
const struct _isr_table_entry *e = &_sw_isr_table[13];
e->isr(e->arg);
return 1 << 13;
}
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
if (mask & (1 << 14)) {
const struct _isr_table_entry *e = &_sw_isr_table[14];
e->isr(e->arg);
return 1 << 14;
}
return 0;
}

371
soc/espressif/common/include/_soc_inthandlers.h
View File

@@ -1,371 +0,0 @@
/*
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x7f) {
if (mask & 0x7) {
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
} else {
if (mask & 0x18) {
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
} else {
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
}
}
} else {
if (mask & 0x780) {
if (mask & 0x180) {
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
} else {
if (mask & BIT(9)) {
mask = BIT(9);
irq = 9;
goto handle_irq;
}
if (mask & BIT(10)) {
mask = BIT(10);
irq = 10;
goto handle_irq;
}
}
} else {
if (mask & 0x3000) {
if (mask & BIT(12)) {
mask = BIT(12);
irq = 12;
goto handle_irq;
}
if (mask & BIT(13)) {
mask = BIT(13);
irq = 13;
goto handle_irq;
}
} else {
if (mask & BIT(17)) {
mask = BIT(17);
irq = 17;
goto handle_irq;
}
if (mask & BIT(18)) {
mask = BIT(18);
irq = 18;
goto handle_irq;
}
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x408800) {
if (mask & BIT(11)) {
mask = BIT(11);
irq = 11;
goto handle_irq;
}
if (mask & BIT(15)) {
mask = BIT(15);
irq = 15;
goto handle_irq;
}
if (mask & BIT(22)) {
mask = BIT(22);
irq = 22;
goto handle_irq;
}
} else {
if (mask & BIT(23)) {
mask = BIT(23);
irq = 23;
goto handle_irq;
}
if (mask & BIT(27)) {
mask = BIT(27);
irq = 27;
goto handle_irq;
}
if (mask & BIT(29)) {
mask = BIT(29);
irq = 29;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(14)) {
mask = BIT(14);
irq = 14;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(16)) {
mask = BIT(16);
irq = 16;
goto handle_irq;
}
if (mask & BIT(26)) {
mask = BIT(26);
irq = 26;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(19)) {
mask = BIT(19);
irq = 19;
goto handle_irq;
}
if (mask & BIT(20)) {
mask = BIT(20);
irq = 20;
goto handle_irq;
}
if (mask & BIT(21)) {
mask = BIT(21);
irq = 21;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x3000000) {
if (mask & BIT(24)) {
mask = BIT(24);
irq = 24;
goto handle_irq;
}
if (mask & BIT(25)) {
mask = BIT(25);
irq = 25;
goto handle_irq;
}
} else {
if (mask & BIT(28)) {
mask = BIT(28);
irq = 28;
goto handle_irq;
}
if (mask & BIT(30)) {
mask = BIT(30);
irq = 30;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}

135
soc/intel/intel_adsp/ace/_soc_inthandlers.h
View File

@@ -1,135 +0,0 @@
/* Copyright (c) 2022 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
/* It is a Non-maskable interrupt handler.
* The non-maskable interrupt have no corresponding bit in INTERRUPT and INTENABLE registers
* so mask parameter is always 0.
*/
_sw_isr_table[8].isr(_sw_isr_table[8].arg);
return 0;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
return 0;
}

269
soc/intel/intel_adsp/cavs/_soc_inthandlers.h
View File

@@ -1,269 +0,0 @@
/*
* Copyright (c) 2020 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x3) {
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
} else {
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x30) {
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
} else {
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x300) {
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
if (mask & BIT(9)) {
mask = BIT(9);
irq = 9;
goto handle_irq;
}
} else {
if (mask & BIT(10)) {
mask = BIT(10);
irq = 10;
goto handle_irq;
}
if (mask & BIT(11)) {
mask = BIT(11);
irq = 11;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(12)) {
mask = BIT(12);
irq = 12;
goto handle_irq;
}
if (mask & BIT(13)) {
mask = BIT(13);
irq = 13;
goto handle_irq;
}
if (mask & BIT(14)) {
mask = BIT(14);
irq = 14;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x18000) {
if (mask & BIT(15)) {
mask = BIT(15);
irq = 15;
goto handle_irq;
}
if (mask & BIT(16)) {
mask = BIT(16);
irq = 16;
goto handle_irq;
}
} else {
if (mask & BIT(17)) {
mask = BIT(17);
irq = 17;
goto handle_irq;
}
if (mask & BIT(18)) {
mask = BIT(18);
irq = 18;
goto handle_irq;
}
if (mask & BIT(19)) {
mask = BIT(19);
irq = 19;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(20)) {
mask = BIT(20);
irq = 20;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}

1
soc/mediatek/mt8xxx/Kconfig
View File

@@ -3,4 +3,3 @@
config SOC_FAMILY_MTK
select XTENSA
select XTENSA_GEN_HANDLERS

178
soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
View File

@@ -1,178 +0,0 @@
/*
* Copyright (c) 2021 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
return 0;
}

178
soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
View File

@@ -1,178 +0,0 @@
/*
* Copyright (c) 2021 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
return 0;
}

393
soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h
View File

@@ -1,393 +0,0 @@
/*
* Copyright (c) 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x70006) {
if (mask & 0x6) {
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
} else {
if (mask & BIT(16)) {
mask = BIT(16);
irq = 16;
goto handle_irq;
}
if (mask & BIT(17)) {
mask = BIT(17);
irq = 17;
goto handle_irq;
}
if (mask & BIT(18)) {
mask = BIT(18);
irq = 18;
goto handle_irq;
}
}
} else {
if (mask & 0x180000) {
if (mask & BIT(19)) {
mask = BIT(19);
irq = 19;
goto handle_irq;
}
if (mask & BIT(20)) {
mask = BIT(20);
irq = 20;
goto handle_irq;
}
} else {
if (mask & BIT(21)) {
mask = BIT(21);
irq = 21;
goto handle_irq;
}
if (mask & BIT(22)) {
mask = BIT(22);
irq = 22;
goto handle_irq;
}
if (mask & BIT(23)) {
mask = BIT(23);
irq = 23;
goto handle_irq;
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x3000038) {
if (mask & 0x18) {
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
} else {
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
if (mask & BIT(24)) {
mask = BIT(24);
irq = 24;
goto handle_irq;
}
if (mask & BIT(25)) {
mask = BIT(25);
irq = 25;
goto handle_irq;
}
}
} else {
if (mask & 0x1c000000) {
if (mask & BIT(26)) {
mask = BIT(26);
irq = 26;
goto handle_irq;
}
if (mask & BIT(27)) {
mask = BIT(27);
irq = 27;
goto handle_irq;
}
if (mask & BIT(28)) {
mask = BIT(28);
irq = 28;
goto handle_irq;
}
} else {
if (mask & BIT(29)) {
mask = BIT(29);
irq = 29;
goto handle_irq;
}
if (mask & BIT(30)) {
mask = BIT(30);
irq = 30;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x7c0) {
if (mask & 0xc0) {
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
} else {
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
if (mask & BIT(9)) {
mask = BIT(9);
irq = 9;
goto handle_irq;
}
if (mask & BIT(10)) {
mask = BIT(10);
irq = 10;
goto handle_irq;
}
}
} else {
if (mask & 0x1800) {
if (mask & BIT(11)) {
mask = BIT(11);
irq = 11;
goto handle_irq;
}
if (mask & BIT(12)) {
mask = BIT(12);
irq = 12;
goto handle_irq;
}
} else {
if (mask & BIT(13)) {
mask = BIT(13);
irq = 13;
goto handle_irq;
}
if (mask & BIT(14)) {
mask = BIT(14);
irq = 14;
goto handle_irq;
}
if (mask & BIT(15)) {
mask = BIT(15);
irq = 15;
goto handle_irq;
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int8(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int9(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int10(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int11(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int12(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int13(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int14(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int15(unsigned int set, unsigned int mask)
{
return 0;
}

178
soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
View File

@@ -1,178 +0,0 @@
/*
* Copyright (c) 2021 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{
return 0;
}

1
soc/nxp/imxrt/imxrt5xx/Kconfig
View File

@@ -24,7 +24,6 @@ config SOC_MIMXRT595S_F1
select XTENSA
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
select XTENSA_CPU_HAS_HIFI3
select XTENSA_GEN_HANDLERS
select XTENSA_RESET_VECTOR
select XTENSA_USE_CORE_CRT1

188
soc/nxp/imxrt/imxrt5xx/f1/include/_soc_inthandlers.h
View File

@@ -1,188 +0,0 @@
/*
* Copyright (c) 2023 Google LLC.
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
/*
* Interrupt masks for every level (RT595 ADSP):
* XCHAL_INTLEVEL1_MASK: 0x0000FFE0
* XCHAL_INTLEVEL2_MASK: 0x00FF0006
* XCHAL_INTLEVEL3_MASK: 0xFF000018
* XCHAL_INTLEVEL4_MASK: 0x00000000
* XCHAL_INTLEVEL5_MASK: 0x00000001
*/
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
mask &= XCHAL_INTLEVEL1_MASK;
for (int i = 5; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
mask &= XCHAL_INTLEVEL2_MASK;
for (int i = 1; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
mask &= XCHAL_INTLEVEL3_MASK;
for (int i = 3; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}

353
soc/nxp/imxrt/imxrt6xx/hifi4/include/_soc_inthandlers.h
View File

@@ -1,353 +0,0 @@
/*
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{
int irq;
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x70006) {
if (mask & 0x6) {
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
} else {
if (mask & BIT(16)) {
mask = BIT(16);
irq = 16;
goto handle_irq;
}
if (mask & BIT(17)) {
mask = BIT(17);
irq = 17;
goto handle_irq;
}
if (mask & BIT(18)) {
mask = BIT(18);
irq = 18;
goto handle_irq;
}
}
} else {
if (mask & 0x180000) {
if (mask & BIT(19)) {
mask = BIT(19);
irq = 19;
goto handle_irq;
}
if (mask & BIT(20)) {
mask = BIT(20);
irq = 20;
goto handle_irq;
}
} else {
if (mask & BIT(21)) {
mask = BIT(21);
irq = 21;
goto handle_irq;
}
if (mask & BIT(22)) {
mask = BIT(22);
irq = 22;
goto handle_irq;
}
if (mask & BIT(23)) {
mask = BIT(23);
irq = 23;
goto handle_irq;
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x7000018) {
if (mask & 0x18) {
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
} else {
if (mask & BIT(24)) {
mask = BIT(24);
irq = 24;
goto handle_irq;
}
if (mask & BIT(25)) {
mask = BIT(25);
irq = 25;
goto handle_irq;
}
if (mask & BIT(26)) {
mask = BIT(26);
irq = 26;
goto handle_irq;
}
}
} else {
if (mask & 0x18000000) {
if (mask & BIT(27)) {
mask = BIT(27);
irq = 27;
goto handle_irq;
}
if (mask & BIT(28)) {
mask = BIT(28);
irq = 28;
goto handle_irq;
}
} else {
if (mask & BIT(29)) {
mask = BIT(29);
irq = 29;
goto handle_irq;
}
if (mask & BIT(30)) {
mask = BIT(30);
irq = 30;
goto handle_irq;
}
if (mask & BIT(31)) {
mask = BIT(31);
irq = 31;
goto handle_irq;
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{
int irq;
if (mask & 0x3e0) {
if (mask & 0x60) {
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
} else {
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
if (mask & BIT(9)) {
mask = BIT(9);
irq = 9;
goto handle_irq;
}
}
} else {
if (mask & 0x1c00) {
if (mask & BIT(10)) {
mask = BIT(10);
irq = 10;
goto handle_irq;
}
if (mask & BIT(11)) {
mask = BIT(11);
irq = 11;
goto handle_irq;
}
if (mask & BIT(12)) {
mask = BIT(12);
irq = 12;
goto handle_irq;
}
} else {
if (mask & BIT(13)) {
mask = BIT(13);
irq = 13;
goto handle_irq;
}
if (mask & BIT(14)) {
mask = BIT(14);
irq = 14;
goto handle_irq;
}
if (mask & BIT(15)) {
mask = BIT(15);
irq = 15;
goto handle_irq;
}
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{
return 0;
}

1
soc/nxp/imxrt/imxrt7xx/hifi1/Kconfig
View File

@@ -6,7 +6,6 @@ config SOC_MIMXRT798S_HIFI1
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
select XTENSA_RESET_VECTOR
select XTENSA_USE_CORE_CRT1
select XTENSA_GEN_HANDLERS
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
select GEN_ISR_TABLES
select HAS_MCUX

1
soc/nxp/imxrt/imxrt7xx/hifi4/Kconfig
View File

@@ -6,7 +6,6 @@ config SOC_MIMXRT798S_HIFI4
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
select XTENSA_RESET_VECTOR
select XTENSA_USE_CORE_CRT1
select XTENSA_GEN_HANDLERS
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
select GEN_ISR_TABLES
select CLOCK_CONTROL