diff --git a/soc/xilinx/zynq7000/xc7zxxx/Kconfig b/soc/xilinx/zynq7000/xc7zxxx/Kconfig index 380c3f99d47..7a94994fd8d 100644 --- a/soc/xilinx/zynq7000/xc7zxxx/Kconfig +++ b/soc/xilinx/zynq7000/xc7zxxx/Kconfig @@ -6,7 +6,7 @@ # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable # -config SOC_SERIES_XILINX_XC7ZXXX +config SOC_SERIES_XC7ZXXX select ARM select CPU_CORTEX_A9 select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER diff --git a/soc/xilinx/zynq7000/xc7zxxx/Kconfig.defconfig b/soc/xilinx/zynq7000/xc7zxxx/Kconfig.defconfig index 5e3b8d8e6b4..b7e4f98dfbe 100644 --- a/soc/xilinx/zynq7000/xc7zxxx/Kconfig.defconfig +++ b/soc/xilinx/zynq7000/xc7zxxx/Kconfig.defconfig @@ -3,10 +3,10 @@ # SPDX-License-Identifier: Apache-2.0 # -if SOC_SERIES_XILINX_XC7ZXXX +if SOC_SERIES_XC7ZXXX # Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core config MP_MAX_NUM_CPUS default 1 -endif # SOC_SERIES_XILINX_XC7ZXXX +endif # SOC_SERIES_XC7ZXXX diff --git a/soc/xilinx/zynq7000/xc7zxxx/Kconfig.soc b/soc/xilinx/zynq7000/xc7zxxx/Kconfig.soc index 49f60066273..6405dc488af 100644 --- a/soc/xilinx/zynq7000/xc7zxxx/Kconfig.soc +++ b/soc/xilinx/zynq7000/xc7zxxx/Kconfig.soc @@ -6,7 +6,7 @@ # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable # -config SOC_SERIES_XILINX_XC7ZXXX +config SOC_SERIES_XC7ZXXX bool select SOC_FAMILY_XILINX_ZYNQ7000 help @@ -15,14 +15,14 @@ config SOC_SERIES_XILINX_XC7ZXXX config SOC_XILINX_XC7Z010 bool - select SOC_SERIES_XILINX_XC7ZXXX + select SOC_SERIES_XC7ZXXX help 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins. config SOC_XILINX_XC7Z015 bool - select SOC_SERIES_XILINX_XC7ZXXX + select SOC_SERIES_XC7ZXXX help 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins, @@ -30,14 +30,14 @@ config SOC_XILINX_XC7Z015 config SOC_XILINX_XC7Z020 bool - select SOC_SERIES_XILINX_XC7ZXXX + select SOC_SERIES_XC7ZXXX help 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins. config SOC_XILINX_XC7Z030 bool - select SOC_SERIES_XILINX_XC7ZXXX + select SOC_SERIES_XC7ZXXX help 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins, @@ -45,7 +45,7 @@ config SOC_XILINX_XC7Z030 config SOC_XILINX_XC7Z035 bool - select SOC_SERIES_XILINX_XC7ZXXX + select SOC_SERIES_XC7ZXXX help 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins, @@ -53,7 +53,7 @@ config SOC_XILINX_XC7Z035 config SOC_XILINX_XC7Z045 bool - select SOC_SERIES_XILINX_XC7ZXXX + select SOC_SERIES_XC7ZXXX help 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins, @@ -61,14 +61,14 @@ config SOC_XILINX_XC7Z045 config SOC_XILINX_XC7Z100 bool - select SOC_SERIES_XILINX_XC7ZXXX + select SOC_SERIES_XC7ZXXX help 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins, up to 16 transceivers. config SOC_SERIES - default "xc7zxxx" if SOC_SERIES_XILINX_XC7ZXXX + default "xc7zxxx" if SOC_SERIES_XC7ZXXX config SOC default "xc7z010" if SOC_XILINX_XC7Z010 diff --git a/soc/xilinx/zynq7000/xc7zxxxs/Kconfig b/soc/xilinx/zynq7000/xc7zxxxs/Kconfig index dece706060a..ecac57425fe 100644 --- a/soc/xilinx/zynq7000/xc7zxxxs/Kconfig +++ b/soc/xilinx/zynq7000/xc7zxxxs/Kconfig @@ -6,7 +6,7 @@ # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable # -config SOC_SERIES_XILINX_XC7ZXXXS +config SOC_SERIES_XC7ZXXXS select ARM select CPU_CORTEX_A9 select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER diff --git a/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.defconfig b/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.defconfig index 310e285fd78..6b4c6558c9a 100644 --- a/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.defconfig +++ b/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.defconfig @@ -3,9 +3,9 @@ # SPDX-License-Identifier: Apache-2.0 # -if SOC_SERIES_XILINX_XC7ZXXXS +if SOC_SERIES_XC7ZXXXS config MP_MAX_NUM_CPUS default 1 -endif # SOC_SERIES_XILINX_XC7ZXXXS +endif # SOC_SERIES_XC7ZXXXS diff --git a/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.soc b/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.soc index 08aec54010a..71a0bf01991 100644 --- a/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.soc +++ b/soc/xilinx/zynq7000/xc7zxxxs/Kconfig.soc @@ -6,7 +6,7 @@ # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable # -config SOC_SERIES_XILINX_XC7ZXXXS +config SOC_SERIES_XC7ZXXXS bool select SOC_FAMILY_XILINX_ZYNQ7000 help @@ -15,14 +15,14 @@ config SOC_SERIES_XILINX_XC7ZXXXS config SOC_XILINX_XC7Z007S bool - select SOC_SERIES_XILINX_XC7ZXXXS + select SOC_SERIES_XC7ZXXXS help 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins. config SOC_XILINX_XC7Z012S bool - select SOC_SERIES_XILINX_XC7ZXXXS + select SOC_SERIES_XC7ZXXXS help 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins, @@ -30,13 +30,13 @@ config SOC_XILINX_XC7Z012S config SOC_XILINX_XC7Z014S bool - select SOC_SERIES_XILINX_XC7ZXXXS + select SOC_SERIES_XC7ZXXXS help 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins. config SOC_SERIES - default "xc7zxxxs" if SOC_SERIES_XILINX_XC7ZXXXS + default "xc7zxxxs" if SOC_SERIES_XC7ZXXXS config SOC default "xc7z007s" if SOC_XILINX_XC7Z007S