soc: riscv: intel_niosv: move and convert to HWMv2
Move to HWMv2 and convert from soc/riscv/intel_niosv SoC family `INTEL_NIOSV` series `NIOSV` SoCs `NIOSV_M` and `NIOSV_G`. Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
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committed by
Carles Cufi
parent
fd1e8cdc30
commit
ecfa192f1b
@@ -1,4 +1,6 @@
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# Copyright (c) 2024 Nordic Semiconductor
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# Copyright (c) 2023-2024 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(${SOC_SERIES})
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@@ -1,4 +1,6 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2023-2024 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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source "soc/soc_legacy/riscv/intel_niosv/*/Kconfig.series"
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rsource "*/Kconfig"
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10
soc/intel/intel_niosv/Kconfig.defconfig
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10
soc/intel/intel_niosv/Kconfig.defconfig
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@@ -0,0 +1,10 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2023-2024 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_INTEL_NIOSV
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rsource "*/Kconfig.defconfig.series"
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endif
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12
soc/intel/intel_niosv/Kconfig.soc
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12
soc/intel/intel_niosv/Kconfig.soc
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@@ -0,0 +1,12 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2023-2024 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_INTEL_NIOSV
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bool
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config SOC_FAMILY
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default "intel_niosv" if SOC_FAMILY_INTEL_NIOSV
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rsource "*/Kconfig.soc"
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22
soc/intel/intel_niosv/niosv/Kconfig
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22
soc/intel/intel_niosv/niosv/Kconfig
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@@ -0,0 +1,22 @@
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# Copyright (C) 2023-2024, Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NIOSV
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select RISCV
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select RISCV_PRIVILEGED
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select ATOMIC_OPERATIONS_BUILTIN
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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config SOC_NIOSV_M
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help
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Intel FPGA NIOSV Microcontroller Core Processor
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config SOC_NIOSV_G
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select RISCV_ISA_EXT_M
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help
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Intel FPGA NIOSV General Purpose Processor
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@@ -1,11 +1,9 @@
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# Copyright (C) 2023, Intel Corporation
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# Copyright (C) 2023-2024, Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NIOSV
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config SOC_SERIES
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default "niosv"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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@@ -18,4 +16,4 @@ config RISCV_GP
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config RISCV_SOC_INTERRUPT_INIT
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default y
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endif # SOC_NIOSV
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endif # SOC_SERIES_NIOSV
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28
soc/intel/intel_niosv/niosv/Kconfig.soc
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28
soc/intel/intel_niosv/niosv/Kconfig.soc
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@@ -0,0 +1,28 @@
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# Copyright (C) 2023-2024, Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NIOSV
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bool
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select SOC_FAMILY_INTEL_NIOSV
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help
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Intel FPGA NIOSV
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config SOC_SERIES
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default "niosv" if SOC_SERIES_NIOSV
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config SOC_NIOSV_M
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bool
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select SOC_SERIES_NIOSV
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help
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Intel FPGA NIOSV Microcontroller Core Processor
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config SOC_NIOSV_G
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bool
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select SOC_SERIES_NIOSV
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help
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Intel FPGA NIOSV General Purpose Processor
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config SOC
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default "niosv_m" if SOC_NIOSV_M
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default "niosv_g" if SOC_NIOSV_G
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7
soc/intel/intel_niosv/soc.yml
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7
soc/intel/intel_niosv/soc.yml
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family:
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- name: intel_niosv
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series:
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- name: niosv
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socs:
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- name: niosv_g
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- name: niosv_m
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@@ -1,15 +0,0 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_INTEL_NIOSV
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bool
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if SOC_FAMILY_INTEL_NIOSV
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config SOC_FAMILY
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string
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default "intel_niosv"
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source "soc/soc_legacy/riscv/intel_niosv/*/Kconfig.soc"
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endif # SOC_FAMILY_INTEL_NIOSV
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@@ -1,4 +0,0 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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source "soc/soc_legacy/riscv/intel_niosv/*/Kconfig.defconfig.series"
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@@ -1,10 +0,0 @@
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# Copyright (C) 2023, Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NIOSV
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bool "INTEL FPGA NIOSV"
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select RISCV
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select RISCV_PRIVILEGED
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select SOC_FAMILY_INTEL_NIOSV
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help
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Enable support for the INTEL FPGA NIOSV.
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@@ -1,27 +0,0 @@
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# Copyright (C) 2023, Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "FPGA NIOSV"
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depends on SOC_SERIES_NIOSV
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config SOC_NIOSV_M
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bool "Intel FPGA NIOSV Microcontroller Core Processor"
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select ATOMIC_OPERATIONS_BUILTIN
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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config SOC_NIOSV_G
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bool "Intel FPGA NIOSV General Purpose Processor"
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select ATOMIC_OPERATIONS_BUILTIN
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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endchoice
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