soc: riscv: intel_niosv: move and convert to HWMv2

Move to HWMv2 and convert from soc/riscv/intel_niosv SoC family
`INTEL_NIOSV` series `NIOSV` SoCs `NIOSV_M` and `NIOSV_G`.

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
This commit is contained in:
Dmitrii Golovanov
2024-02-11 12:15:43 +01:00
committed by Carles Cufi
parent fd1e8cdc30
commit ecfa192f1b
14 changed files with 87 additions and 62 deletions

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@@ -1,4 +1,6 @@
# Copyright (c) 2024 Nordic Semiconductor
# Copyright (c) 2023-2024 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(${SOC_SERIES})

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@@ -1,4 +1,6 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# Copyright (c) 2023-2024 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/riscv/intel_niosv/*/Kconfig.series"
rsource "*/Kconfig"

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@@ -0,0 +1,10 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# Copyright (c) 2023-2024 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INTEL_NIOSV
rsource "*/Kconfig.defconfig.series"
endif

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@@ -0,0 +1,12 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# Copyright (c) 2023-2024 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_INTEL_NIOSV
bool
config SOC_FAMILY
default "intel_niosv" if SOC_FAMILY_INTEL_NIOSV
rsource "*/Kconfig.soc"

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@@ -0,0 +1,22 @@
# Copyright (C) 2023-2024, Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NIOSV
select RISCV
select RISCV_PRIVILEGED
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
config SOC_NIOSV_M
help
Intel FPGA NIOSV Microcontroller Core Processor
config SOC_NIOSV_G
select RISCV_ISA_EXT_M
help
Intel FPGA NIOSV General Purpose Processor

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@@ -1,11 +1,9 @@
# Copyright (C) 2023, Intel Corporation
# Copyright (C) 2023-2024, Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_NIOSV
config SOC_SERIES
default "niosv"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
@@ -18,4 +16,4 @@ config RISCV_GP
config RISCV_SOC_INTERRUPT_INIT
default y
endif # SOC_NIOSV
endif # SOC_SERIES_NIOSV

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@@ -0,0 +1,28 @@
# Copyright (C) 2023-2024, Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NIOSV
bool
select SOC_FAMILY_INTEL_NIOSV
help
Intel FPGA NIOSV
config SOC_SERIES
default "niosv" if SOC_SERIES_NIOSV
config SOC_NIOSV_M
bool
select SOC_SERIES_NIOSV
help
Intel FPGA NIOSV Microcontroller Core Processor
config SOC_NIOSV_G
bool
select SOC_SERIES_NIOSV
help
Intel FPGA NIOSV General Purpose Processor
config SOC
default "niosv_m" if SOC_NIOSV_M
default "niosv_g" if SOC_NIOSV_G

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@@ -0,0 +1,7 @@
family:
- name: intel_niosv
series:
- name: niosv
socs:
- name: niosv_g
- name: niosv_m

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@@ -1,15 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_INTEL_NIOSV
bool
if SOC_FAMILY_INTEL_NIOSV
config SOC_FAMILY
string
default "intel_niosv"
source "soc/soc_legacy/riscv/intel_niosv/*/Kconfig.soc"
endif # SOC_FAMILY_INTEL_NIOSV

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@@ -1,4 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/riscv/intel_niosv/*/Kconfig.defconfig.series"

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@@ -1,10 +0,0 @@
# Copyright (C) 2023, Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NIOSV
bool "INTEL FPGA NIOSV"
select RISCV
select RISCV_PRIVILEGED
select SOC_FAMILY_INTEL_NIOSV
help
Enable support for the INTEL FPGA NIOSV.

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@@ -1,27 +0,0 @@
# Copyright (C) 2023, Intel Corporation
# SPDX-License-Identifier: Apache-2.0
choice
prompt "FPGA NIOSV"
depends on SOC_SERIES_NIOSV
config SOC_NIOSV_M
bool "Intel FPGA NIOSV Microcontroller Core Processor"
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
config SOC_NIOSV_G
bool "Intel FPGA NIOSV General Purpose Processor"
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
endchoice