michael/zephyr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

soc: ae350: Port to HWMv2

Browse Source 
Ports the ae350 SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Jamie McCrae
2024-02-15 08:58:40 +00:00
committed by Carles Cufi
parent 282204758a
commit ef82a8255c
33 changed files with 55 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
soc/CMakeLists.txt
View File

@@ -9,6 +9,8 @@ if(_SOC_IS_IN_TREE)
endif() endif()
unset(_SOC_IS_IN_TREE) unset(_SOC_IS_IN_TREE)
add_subdirectory(common)
if(HWMv1) if(HWMv1)
if(EXISTS ${SOC_DIR}/${ARCH}/CMakeLists.txt) if(EXISTS ${SOC_DIR}/${ARCH}/CMakeLists.txt)
add_subdirectory(${SOC_DIR}/${ARCH} soc/${ARCH}) add_subdirectory(${SOC_DIR}/${ARCH} soc/${ARCH})

3
soc/Kconfig
View File

@@ -15,6 +15,9 @@ osource "soc/soc_legacy/$(ARCH)/Kconfig"
# Source Zephyr Kconfig specifics from SoC roots. # Source Zephyr Kconfig specifics from SoC roots.
osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig" osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig"
# Source common Kconfig file
osource "soc/common/Kconfig"
module = SOC module = SOC
module-str = SOC module-str = SOC
source "subsys/logging/Kconfig.template.log_config" source "subsys/logging/Kconfig.template.log_config"

0
soc/soc_legacy/riscv/andes_v5/CMakeLists.txt → soc/andes/CMakeLists.txt
View File

2
soc/soc_legacy/riscv/andes_v5/Kconfig.soc → soc/andes/Kconfig
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2024 Nordic Semiconductor ASA # Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/riscv/andes_v5/*/Kconfig.series" rsource "*/Kconfig"

9
soc/soc_legacy/riscv/andes_v5/Kconfig → soc/andes/Kconfig.defconfig
View File

@@ -1,15 +1,8 @@
# Copyright (c) 2024 Nordic Semiconductor ASA # Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_ANDES_V5
bool
if SOC_FAMILY_ANDES_V5 if SOC_FAMILY_ANDES_V5
config SOC_FAMILY rsource "*/Kconfig.defconfig"
string
default "andes_v5"
source "soc/soc_legacy/riscv/andes_v5/*/Kconfig.soc"
endif # SOC_FAMILY_ANDES_V5 endif # SOC_FAMILY_ANDES_V5

10
soc/andes/Kconfig.soc Normal file
View File

@@ -0,0 +1,10 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_ANDES_V5
bool
config SOC_FAMILY
default "andes_v5" if SOC_FAMILY_ANDES_V5
rsource "*/Kconfig.soc"

0
soc/soc_legacy/riscv/andes_v5/ae350/CMakeLists.txt → soc/andes/ae350/CMakeLists.txt
View File

10
soc/soc_legacy/riscv/andes_v5/ae350/Kconfig.soc → soc/andes/ae350/Kconfig
View File

@@ -1,12 +1,12 @@
# Copyright (c) 2021 Andes Technology Corporation # Copyright (c) 2021 Andes Technology Corporation
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
choice config SOC_SERIES_ANDES_AE350
prompt "Andes V5 SoC Selection" select RISCV
depends on SOC_SERIES_ANDES_AE350 select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
config SOC_ANDES_AE350 config SOC_ANDES_AE350
bool "Andes AE350 SoC implementation"
select ATOMIC_OPERATIONS_BUILTIN select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR select INCLUDE_RESET_VECTOR
select RISCV_ISA_EXT_M select RISCV_ISA_EXT_M
@@ -16,8 +16,6 @@ config SOC_ANDES_AE350
select CPU_HAS_ICACHE select CPU_HAS_ICACHE
select RISCV_PMP select RISCV_PMP
endchoice
if SOC_SERIES_ANDES_AE350 if SOC_SERIES_ANDES_AE350
choice choice

5
soc/soc_legacy/riscv/andes_v5/ae350/Kconfig.defconfig.series → soc/andes/ae350/Kconfig.defconfig
View File

@@ -6,10 +6,7 @@ if SOC_SERIES_ANDES_AE350
# Kconfig picks the first default with a satisfied condition. # Kconfig picks the first default with a satisfied condition.
# SoC defaults should be parsed before SoC Series defaults, because SoCs usually # SoC defaults should be parsed before SoC Series defaults, because SoCs usually
# overrides SoC Series values. # overrides SoC Series values.
source "soc/soc_legacy/riscv/andes_v5/ae350/Kconfig.defconfig.ae*" rsource "Kconfig.defconfig.ae*"
config SOC_SERIES
default "ae350"
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
default 60000000 default 60000000

3
soc/soc_legacy/riscv/andes_v5/ae350/Kconfig.defconfig.ae350 → soc/andes/ae350/Kconfig.defconfig.ae350
View File

@@ -3,9 +3,6 @@
if SOC_ANDES_AE350 if SOC_ANDES_AE350
config SOC
default "ae350"
config SYS_CLOCK_TICKS_PER_SEC config SYS_CLOCK_TICKS_PER_SEC
default 100 if (!ICACHE || XIP) default 100 if (!ICACHE || XIP)

20
soc/andes/ae350/Kconfig.soc Normal file
View File

@@ -0,0 +1,20 @@
# Copyright (c) 2021 Andes Technology Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_ANDES_AE350
bool
select SOC_FAMILY_ANDES_V5
help
Andes V5 AE350 SoC Series Implementation"
config SOC_ANDES_AE350
bool
select SOC_SERIES_ANDES_AE350
help
Andes AE350 SoC implementation"
config SOC_SERIES
default "ae350" if SOC_SERIES_ANDES_AE350
config SOC
default "ae350" if SOC_ANDES_AE350

0
soc/soc_legacy/riscv/andes_v5/ae350/common_linker/execit.ld → soc/andes/ae350/common_linker/execit.ld
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/common_linker/init.ld → soc/andes/ae350/common_linker/init.ld
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/common_linker/ram_start_nonzero.ld → soc/andes/ae350/common_linker/ram_start_nonzero.ld
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/l2_cache.c → soc/andes/ae350/l2_cache.c
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/linker.ld → soc/andes/ae350/linker.ld
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/pma.c → soc/andes/ae350/pma.c
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/soc_context.h → soc/andes/ae350/soc_context.h
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/soc_irq.S → soc/andes/ae350/soc_irq.S
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/soc_offsets.h → soc/andes/ae350/soc_offsets.h
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/soc_v5.h → soc/andes/ae350/soc_v5.h
View File

0
soc/soc_legacy/riscv/andes_v5/ae350/start.S → soc/andes/ae350/start.S
View File

6
soc/andes/soc.yml Normal file
View File

@@ -0,0 +1,6 @@
family:
- name: andes_v5
series:
- name: ae350
socs:
- name: ae350

2
soc/soc_legacy/riscv/andes_v5/Kconfig.defconfig → soc/common/CMakeLists.txt
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2024 Nordic Semiconductor ASA # Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/riscv/andes_v5/*/Kconfig.defconfig.series" add_subdirectory_ifdef(CONFIG_RISCV_PRIVILEGED riscv-privileged)

8
soc/soc_legacy/riscv/common/Kconfig → soc/common/Kconfig
View File

@@ -1,4 +1,8 @@
# Copyright (c) 2024 Nordic Semiconductor ASA # Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
#
source "soc/soc_legacy/riscv/common/riscv-privileged/Kconfig" if RISCV_PRIVILEGED
rsource "riscv-privileged/Kconfig"
endif # RISCV_PRIVILEGED

0
soc/soc_legacy/riscv/common/riscv-privileged/CMakeLists.txt → soc/common/riscv-privileged/CMakeLists.txt
View File

0
soc/soc_legacy/riscv/common/riscv-privileged/Kconfig → soc/common/riscv-privileged/Kconfig
View File

0
soc/soc_legacy/riscv/common/riscv-privileged/soc_common_irq.c → soc/common/riscv-privileged/soc_common_irq.c
View File

0
soc/soc_legacy/riscv/common/riscv-privileged/soc_irq.S → soc/common/riscv-privileged/soc_irq.S
View File

0
soc/soc_legacy/riscv/common/riscv-privileged/vector.S → soc/common/riscv-privileged/vector.S
View File

2
soc/soc_legacy/riscv/CMakeLists.txt
View File

@@ -1,7 +1,5 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
add_subdirectory(common)
if(SOC_FAMILY) if(SOC_FAMILY)
add_subdirectory(${SOC_FAMILY}) add_subdirectory(${SOC_FAMILY})
else() else()

11
soc/soc_legacy/riscv/andes_v5/ae350/Kconfig.series
View File

@@ -1,11 +0,0 @@
# Copyright (c) 2021 Andes Technology Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_ANDES_AE350
bool "Andes V5 AE350 SoC Series Implementation"
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select SOC_FAMILY_ANDES_V5
help
Enable support for Andes V5 AE350 SoC Series

1
soc/soc_legacy/riscv/common/CMakeLists.txt
View File

@@ -1 +0,0 @@
add_subdirectory_ifdef(CONFIG_RISCV_PRIVILEGED riscv-privileged)