soc: ast10x0: Port to HWMv2

Ports the ast10x0 SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/aspeed/Kconfig

@@ -2,4 +2,7 @@
 #
 # Copyright (c) 2021 ASPEED Technology Inc.
 
-source "soc/soc_legacy/arm/aspeed/*/Kconfig.defconfig.series"
+config SOC_FAMILY_ASPEED
+	select PLATFORM_SPECIFIC_INIT
+
+rsource "*/Kconfig"

soc/aspeed/Kconfig.defconfig

@@ -2,4 +2,4 @@
 #
 # Copyright (c) 2021 ASPEED Technology Inc.
 
-source "soc/soc_legacy/arm/aspeed/*/Kconfig.series"
+rsource "*/Kconfig.defconfig"

soc/aspeed/Kconfig.soc

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2021 ASPEED Technology Inc.
+
+config SOC_FAMILY_ASPEED
+	bool
+
+config SOC_FAMILY
+	default "aspeed" if SOC_FAMILY_ASPEED
+
+rsource "*/Kconfig.soc"

soc/aspeed/ast10x0/CMakeLists.txt

@@ -4,12 +4,13 @@
 #
 
 zephyr_sources(soc.c)
-zephyr_include_directories(${ZEPHYR_BASE}/soc/soc_legacy/arm/common/cortex_m)
+zephyr_include_directories(.)
 zephyr_linker_sources(ROM_START SORT_KEY 0x1sboot sboot.ld)
 zephyr_linker_sources(RAM_SECTIONS nocache.ld)
 
+string(TOUPPER "${SOC_NAME}" soc_name_upper)
 set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-  COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/${SOC_SERIES}/tools/gen_uart_booting_image.py
+  COMMAND ${PYTHON_EXECUTABLE} ${SOC_${soc_name_upper}_DIR}/${SOC_SERIES}/tools/gen_uart_booting_image.py
   ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
   ${PROJECT_BINARY_DIR}/uart_${CONFIG_KERNEL_BIN_NAME}.bin
 )

soc/aspeed/ast10x0/Kconfig

@@ -2,14 +2,19 @@
 #
 # Copyright (c) 2021 ASPEED Technology Inc.
 
-choice
-	prompt "ASPEED AST10X0 Selection"
-	depends on SOC_SERIES_AST10X0
+config SOC_SERIES_AST10X0
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select SYSCON
+	select CACHE
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+	select CACHE_MANAGEMENT
+	select CACHE_ASPEED
 
-config SOC_AST1030
-	bool "AST1030"
-
-endchoice
+if SOC_SERIES_AST10X0
 
 config SRAM_NC_SIZE
 	int "noncached SRAM Size in kB"
@@ -24,3 +29,5 @@ config SRAM_NC_BASE_ADDRESS
 	  The non-cached SRAM base address. The default value comes from from
 	  reg[1] of /chosen/zephyr,sram in devicetree. The user should
 	  generally avoid changing it via menuconfig or in configuration files.
+
+endif # SOC_SERIES_AST10X0

soc/aspeed/ast10x0/Kconfig.defconfig

@@ -4,10 +4,7 @@
 
 if SOC_SERIES_AST10X0
 
-source "soc/soc_legacy/arm/aspeed/ast10x0/Kconfig.defconfig.ast10*0"
-
-config SOC_SERIES
-	default "ast10x0"
+rsource "Kconfig.defconfig.ast10*0"
 
 config ICACHE_LINE_SIZE
 	default 32

soc/aspeed/ast10x0/Kconfig.soc

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2021 ASPEED Technology Inc.
+
+config SOC_SERIES_AST10X0
+	bool
+	select SOC_FAMILY_ASPEED
+	help
+	  Enable support for ASPEED AST10X0 series
+
+config SOC_AST1030
+	bool
+	select SOC_SERIES_AST10X0
+	help
+	  AST1030
+
+config SOC_SERIES
+	default "ast10x0" if SOC_SERIES_AST10X0
+
+config SOC
+	default "ast1030" if SOC_AST1030

soc/aspeed/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: ast10x0
+  socs:
+  - name: ast1030

soc/soc_legacy/arm/aspeed/Kconfig

@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-#
-# Copyright (c) 2021 ASPEED Technology Inc.
-
-config SOC_FAMILY_ASPEED
-	select PLATFORM_SPECIFIC_INIT
-	bool
-
-if SOC_FAMILY_ASPEED
-
-config SOC_FAMILY
-	string
-	default "aspeed"
-
-source "soc/soc_legacy/arm/aspeed/*/Kconfig.soc"
-
-endif # SOC_FAMILY_ASPEED

soc/soc_legacy/arm/aspeed/ast10x0/Kconfig.series

@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-#
-# Copyright (c) 2021 ASPEED Technology Inc.
-
-config SOC_SERIES_AST10X0
-	bool "Aspeed AST10X0 Series"
-	select ARM
-	select CPU_CORTEX_M4
-	select CPU_HAS_FPU
-	select CPU_HAS_ARM_MPU
-	select SOC_FAMILY_ASPEED
-	select SYSCON
-	select CACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_ICACHE
-	select CACHE_MANAGEMENT
-	select CACHE_ASPEED
-	help
-	  Enable support for ASPEED AST10X0 series