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boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2

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Converts the board to hwmv2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Jamie McCrae
2024-02-06 14:45:37 +00:00
committed by Carles Cufi
parent ff202daa8e
commit f5792b05e7
21 changed files with 84 additions and 153 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r
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@@ -2,5 +2,5 @@
# SPDX-License-Identifier: Apache-2.0
config BOARD_FVP_BASER_AEMV8R
select SOC_SERIES_FVP_AEMV8R
select SOC_FVP_AEMV8R_AARCH64
select SOC_FVP_AEMV8R_AARCH64 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64_SMP
select SOC_FVP_AEMV8R_AARCH32 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32_SMP

97
boards/arm/fvp_baser_aemv8r/board.cmake
View File

@@ -5,35 +5,70 @@ set(SUPPORTED_EMU_PLATFORMS armfvp)
set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
set(ARMFVP_MIN_VERSION 11.16.16)
set(ARMFVP_FLAGS
-C cluster0.has_aarch64=1
-C cluster0.VMSA_supported=0
-C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
-C cluster0.gicv3.cpuintf-mmap-access-level=2
-C cluster0.gicv3.SRE-enable-action-on-mmap=2
-C cluster0.gicv3.SRE-EL2-enable-RAO=1
-C cluster0.gicv3.extended-interrupt-range-support=1
-C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
-C gic_distributor.has-two-security-states=0
-C bp.refcounter.non_arch_start_at_default=1
# UART0 config
-C bp.pl011_uart0.out_file=-
-C bp.pl011_uart0.unbuffered_output=1
-C bp.terminal_0.start_telnet=0
# UART1 config
-C bp.pl011_uart1.out_file=-
-C bp.pl011_uart1.unbuffered_output=1
-C bp.terminal_1.start_telnet=0
# UART2 config
-C bp.pl011_uart2.out_file=-
-C bp.pl011_uart2.unbuffered_output=1
-C bp.terminal_2.start_telnet=0
# UART3 config
-C bp.pl011_uart3.out_file=-
-C bp.pl011_uart3.unbuffered_output=1
-C bp.terminal_3.start_telnet=0
if(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64)
set(ARMFVP_FLAGS
-C cluster0.has_aarch64=1
-C cluster0.VMSA_supported=0
-C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
-C cluster0.gicv3.cpuintf-mmap-access-level=2
-C cluster0.gicv3.SRE-enable-action-on-mmap=2
-C cluster0.gicv3.SRE-EL2-enable-RAO=1
-C cluster0.gicv3.extended-interrupt-range-support=1
-C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
-C gic_distributor.has-two-security-states=0
-C bp.refcounter.non_arch_start_at_default=1
# UART0 config
-C bp.pl011_uart0.out_file=-
-C bp.pl011_uart0.unbuffered_output=1
-C bp.terminal_0.start_telnet=0
# UART1 config
-C bp.pl011_uart1.out_file=-
-C bp.pl011_uart1.unbuffered_output=1
-C bp.terminal_1.start_telnet=0
# UART2 config
-C bp.pl011_uart2.out_file=-
-C bp.pl011_uart2.unbuffered_output=1
-C bp.terminal_2.start_telnet=0
# UART3 config
-C bp.pl011_uart3.out_file=-
-C bp.pl011_uart3.unbuffered_output=1
-C bp.terminal_3.start_telnet=0
-C bp.vis.disable_visualisation=1
-C bp.vis.rate_limit-enable=0
-C cache_state_modelled=1
)
-C bp.vis.disable_visualisation=1
-C bp.vis.rate_limit-enable=0
-C cache_state_modelled=1
)
elseif(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32)
set(ARMFVP_FLAGS
-C cluster0.has_aarch64=0
-C cluster0.VMSA_supported=0
-C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
-C cluster0.gicv3.cpuintf-mmap-access-level=2
-C cluster0.gicv3.SRE-enable-action-on-mmap=2
-C cluster0.gicv3.SRE-EL2-enable-RAO=1
-C cluster0.gicv3.extended-interrupt-range-support=1
-C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
-C gic_distributor.has-two-security-states=0
-C bp.refcounter.non_arch_start_at_default=1
# UART0 config
-C bp.pl011_uart0.out_file=-
-C bp.pl011_uart0.unbuffered_output=1
-C bp.terminal_0.start_telnet=0
# UART1 config
-C bp.pl011_uart1.out_file=-
-C bp.pl011_uart1.unbuffered_output=1
-C bp.terminal_1.start_telnet=0
# UART2 config
-C bp.pl011_uart2.out_file=-
-C bp.pl011_uart2.unbuffered_output=1
-C bp.terminal_2.start_telnet=0
# UART3 config
-C bp.pl011_uart3.out_file=-
-C bp.pl011_uart3.unbuffered_output=1
-C bp.terminal_3.start_telnet=0
-C bp.vis.disable_visualisation=1
-C bp.vis.rate_limit-enable=0
-C cache_state_modelled=0
)
endif()

3
boards/arm/fvp_baser_aemv8r/board.yml
View File

@@ -5,3 +5,6 @@ board:
- name: fvp_aemv8r_aarch64
variants:
- name: 'smp'
- name: fvp_aemv8r_aarch32
variants:
- name: 'smp'

0
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/doc/index.rst → boards/arm/fvp_baser_aemv8r/doc/aarch32.rst
View File

0
boards/arm/fvp_baser_aemv8r/doc/index.rst → boards/arm/fvp_baser_aemv8r/doc/aarch64.rst
View File

0
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.dts → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts
View File

2
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml
View File

@@ -2,7 +2,7 @@
# Copyright (c) 2022 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
identifier: fvp_baser_aemv8r_aarch32
identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32
name: FVP Emulation FVP_BaseR_AEMv8R AArch32
arch: arm
type: sim

3
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_defconfig → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig
View File

@@ -2,9 +2,6 @@
# Copyright (c) 2022 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y
CONFIG_SOC_FVP_AEMV8R_AARCH32=y
CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y
CONFIG_ARM_MPU=y
CONFIG_ISR_STACK_SIZE=1024

2
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.dts → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts
View File

@@ -5,4 +5,4 @@
/dts-v1/;
#include "fvp_baser_aemv8r_aarch32.dts"
#include "fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts"

2
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.yaml → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml
View File

@@ -1,7 +1,7 @@
# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
# SPDX-License-Identifier: Apache-2.0
identifier: fvp_baser_aemv8r_aarch32_smp
identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp
name: FVP Emulation FVP_BaseR_AEMv8R AArch32 (SMP)
arch: arm
type: sim

6
boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig Normal file
View File

@@ -0,0 +1,6 @@
# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
# SPDX-License-Identifier: Apache-2.0
CONFIG_USE_SWITCH=y
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=4

0
boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r.dts → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts
View File

2
boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml
View File

@@ -1,7 +1,7 @@
# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
# SPDX-License-Identifier: Apache-2.0
identifier: fvp_baser_aemv8r
identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64
name: FVP Emulation FVP_BaseR_AEMv8R
arch: arm64
type: sim

0
boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig → boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_defconfig
View File

2
boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts
View File

@@ -3,4 +3,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "fvp_baser_aemv8r.dts"
#include "fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts"

2
boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml
View File

@@ -1,7 +1,7 @@
# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
# SPDX-License-Identifier: Apache-2.0
identifier: fvp_baser_aemv8r//smp
identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp
name: FVP Emulation FVP_BaseR_AEMv8R (SMP)
arch: arm64
type: sim

21
boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig
View File

@@ -1,26 +1,7 @@
# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
# SPDX-License-Identifier: Apache-2.0
# Cache management
CONFIG_CACHE_MANAGEMENT=y
CONFIG_THREAD_STACK_INFO=y
# Enable Timer and Sys clock
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_ARM_ARCH_TIMER=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable serial port
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable simulate cpu power management
# Enable simulated CPU power management
CONFIG_SOC_FVP_AEMV8R_SIMULATE_CPU_PM=y
CONFIG_PM_CPU_OPS=y
CONFIG_PM_CPU_OPS_PSCI=n

7
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/Kconfig.board
View File

@@ -1,7 +0,0 @@
# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
# Copyright (c) 2022 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
config BOARD_FVP_BASER_AEMV8R_AARCH32
bool "FVP BaseR AEMv8R AArch32 simulation board"
depends on SOC_FVP_AEMV8R_AARCH32

13
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig
View File

@@ -1,13 +0,0 @@
# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
# Copyright (c) 2022 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
if BOARD_FVP_BASER_AEMV8R_AARCH32
config BUILD_OUTPUT_BIN
default y
config BOARD
default "fvp_baser_aemv8r_aarch32"
endif # BOARD_FVP_BASER_AEMV8R_AARCH32

39
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/board.cmake
View File

@@ -1,39 +0,0 @@
# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
# Copyright (c) 2022 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
set(SUPPORTED_EMU_PLATFORMS armfvp)
set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
set(ARMFVP_FLAGS
-C cluster0.has_aarch64=0
-C cluster0.VMSA_supported=0
-C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
-C cluster0.gicv3.cpuintf-mmap-access-level=2
-C cluster0.gicv3.SRE-enable-action-on-mmap=2
-C cluster0.gicv3.SRE-EL2-enable-RAO=1
-C cluster0.gicv3.extended-interrupt-range-support=1
-C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
-C gic_distributor.has-two-security-states=0
-C bp.refcounter.non_arch_start_at_default=1
# UART0 config
-C bp.pl011_uart0.out_file=-
-C bp.pl011_uart0.unbuffered_output=1
-C bp.terminal_0.start_telnet=0
# UART1 config
-C bp.pl011_uart1.out_file=-
-C bp.pl011_uart1.unbuffered_output=1
-C bp.terminal_1.start_telnet=0
# UART2 config
-C bp.pl011_uart2.out_file=-
-C bp.pl011_uart2.unbuffered_output=1
-C bp.terminal_2.start_telnet=0
# UART3 config
-C bp.pl011_uart3.out_file=-
-C bp.pl011_uart3.unbuffered_output=1
-C bp.terminal_3.start_telnet=0
-C bp.vis.disable_visualisation=1
-C bp.vis.rate_limit-enable=0
-C cache_state_modelled=0
)

32
boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig
View File

@@ -1,32 +0,0 @@
# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y
CONFIG_SOC_FVP_AEMV8R_AARCH32=y
CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y
CONFIG_ARM_MPU=y
CONFIG_ISR_STACK_SIZE=1024
CONFIG_THREAD_STACK_INFO=y
# Enable Timer and Sys clock
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_ARM_ARCH_TIMER=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable serial port
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_CACHE_MANAGEMENT=y
CONFIG_USE_SWITCH=y
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=4
CONFIG_DCACHE=n